On Tue, Sep 30, 2014 at 11:16 PM, Paolo Bonzini wrote:
> Il 30/09/2014 17:09, Zhi Yong Wu ha scritto:
>>> >
>>> > So the problem seems to be with "-Wl,-fstack-protector-all". Where does
>>> > it come from? QEMU or some pkg-config file?
>>> >
>>> > Does it work if you configure with the --disable
On 09/30/2014 05:59 AM, Markus Armbruster wrote:
> IDs have long spread beyond QemuOpts: not everything with an ID
> necessarily goes through QemuOpts. Commit 9aebf3b is about such a
> case: block layer names are meant to be well-formed IDs, but some of
> them don't go through QemuOpts, and thus w
Update our copy of libvixl to upstream 1.6. There are no
changes of any particular interest to QEMU, so this is simply
keeping up with current upstream.
Signed-off-by: Peter Maydell
---
disas/arm-a64.cc | 2 +-
disas/libvixl/README | 2 +-
disas/libvixl/
On 09/29/2014 09:02 PM, arei.gong...@huawei.com wrote:
> From: Gonglei
>
> Add a new "description" field to DevicePropertyInfo.
> The descriptions can serve as documentation in the code,
> and they can be used to provide better help. For example:
>
> ---
> qapi-schema.json | 4 +++-
> qdev-mo
Users of virtio-serial may want to know when a port becomes writable. A
port can stop accepting writes if the guest port is open but not being
read from. In this case, data gets queued up in the virtqueue, and
after the vq is full, writes to the port do not succeed.
When the guest reads off a vq
On 30 September 2014 17:02, Amit Shah wrote:
> Users of virtio-serial may want to know when a port becomes writable. A
> port can stop accepting writes if the guest port is open but not being
> read from. In this case, data gets queued up in the virtqueue, and
> after the vq is full, writes to t
Users of virtio-serial may want to know when a port becomes writable. A
port can stop accepting writes if the guest port is open but not being
read from. In this case, data gets queued up in the virtqueue, and
after the vq is full, writes to the port do not succeed.
When the guest reads off a vq
On 09/30/2014 03:54 AM, Markus Armbruster wrote:
John Snow writes:
This patch implements the backend for the Q35 board
for us to be able to pick up and use drives defined
by the -cdrom, -hda, or -drive if=ide shorthand options.
Signed-off-by: John Snow
---
hw/i386/pc_q35.c | 4
hw
Eric Blake writes:
> A future patch will be using a 'name':{dictionary} entry in the
> QAPI schema to specify a default value for an optional argument;
> but existing use of inline substructs conflicts with that goal.
> This patch fixes one of only two commands relying on nested
> subtypes, by br
On 30 September 2014 13:24, Paolo Bonzini wrote:
> The following changes since commit 380f649e02f9545159dc3158d7c1b2e70c1005e3:
>
> Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request'
> into staging (2014-09-23 12:08:55 +0100)
>
> are available in the git repository at:
>
>
Hi:
I am running qemu-kvm version 1.0
($kvm -version
QEMU emulator version 1.0 (qemu-kvm-1.0), Copyright (c) 2003-2008 Fabrice
Bellard)
When I start a VM with 4 vcpus, I see about 8 threads. (the thread count
varies ...)
1118 1118 ?00:00:00 kvm-irqfd-clean
*8767 8767 pts/400:03:1
Eric Blake writes:
> A future patch will be using a 'name':{dictionary} entry in the
> QAPI schema to specify a default value for an optional argument;
> but existing use of inline substructs conflicts with that goal.
> Now that all commands have been fixed to avoid inline substructs,
Suggest s/
This is an attempt to write unit tests for the target-i386/cpu.c code. By now, I
just implemented 3 simple test cases, to ensure X86CPU objects can be created,
and to ensure the CPU features are set properly depending on the CPU model
table.
This needs to be applied after:
From: Eduardo Habko
To make unit tests that depend on target-specific files, use
check-unit--y and test-obj--y.
Note that the qtest test cases were per-*arch* (e.g. i386, mips, ppc),
not per-*target* (e.g. i386-softmmu, x86_64-linux-user), because they
implicitly apply only to the -softmmu targets. Target-specific un
Other test code will use the function.
Signed-off-by: Eduardo Habkost
---
tests/Makefile | 1 +
tests/coroutine-stub.c | 13 +
tests/test-vmstate.c | 11 ---
3 files changed, 14 insertions(+), 11 deletions(-)
create mode 100644 tests/coroutine-stub.c
diff --git a
Signed-off-by: Eduardo Habkost
---
tests/test-x86-cpu.c | 25 +
1 file changed, 25 insertions(+)
diff --git a/tests/test-x86-cpu.c b/tests/test-x86-cpu.c
index 9227e20..e8e9a74 100644
--- a/tests/test-x86-cpu.c
+++ b/tests/test-x86-cpu.c
@@ -30,6 +30,30 @@ static void tes
Signed-off-by: Eduardo Habkost
---
tests/test-x86-cpu.c | 28
1 file changed, 28 insertions(+)
diff --git a/tests/test-x86-cpu.c b/tests/test-x86-cpu.c
index e8e9a74..afd5088 100644
--- a/tests/test-x86-cpu.c
+++ b/tests/test-x86-cpu.c
@@ -54,6 +54,33 @@ static void
Instead of using a test-specific hack to add -I$(SRC_PATH)/target-i386, add
test-x86-cpuid to $(test-obj-x86_64-softmmu-y).
Signed-off-by: Eduardo Habkost
---
tests/Makefile | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/tests/Makefile b/tests/Makefile
index ea17838..9
This will make it easier to write unit tests for the feature
initialization logic.
Signed-off-by: Eduardo Habkost
---
target-i386/cpu.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index e7bf9de..b1eb0cb 100644
--- a/targe
The unit test includes target-i386/cpu.c instead of simply linking
against cpu.o because the test code will use static variables/functions
from cpu.c.
Reasoning for each object file included in the test binary:
* qom/cpu.o - for TYPE_CPU. Dependencies:
* qom/qom-qobject.o
* qom/qdev.o - for T
On Tue, Sep 30, 2014 at 12:46 AM, Benoît Canet wrote:
> The Friday 26 Sep 2014 à 18:19:55 (+0300), Boris Sukholitko wrote :
>> This patchset is a small rebase of the 9p live migration patches made a year
>> ago by Benoit Canet.
>>
>> See http://lists.gnu.org/archive/html/qemu-devel/2013-04/msg0219
On Tue, Sep 30, 2014 at 12:48 AM, Benoît Canet wrote:
> The Friday 26 Sep 2014 à 18:19:56 (+0300), Boris Sukholitko wrote :
>
>
>> This patch is a rebase of Aneesh Kumar's and Benoit Canet's previous
>> work.
>>
>> Signed-off-by: Boris Sukholitko
>
> If Aneesh and me worked on this you should als
The Tuesday 30 Sep 2014 à 22:08:12 (+0300), Boris Sukholitko wrote :
> On Tue, Sep 30, 2014 at 12:46 AM, Benoît Canet
> wrote:
> > The Friday 26 Sep 2014 à 18:19:55 (+0300), Boris Sukholitko wrote :
> >> This patchset is a small rebase of the 9p live migration patches made a
> >> year
> >> ago b
This is consistent with how VirtIOFOOConf variables are named
elsewhere, and makes blk available for BlockBackend variables.
Signed-off-by: Markus Armbruster
Reviewed-by: Max Reitz
---
hw/block/dataplane/virtio-blk.c | 33 ++-
hw/block/dataplane/virtio-blk.h | 2 +-
hw/
Signed-off-by: Markus Armbruster
Reviewed-by: Benoît Canet
Reviewed-by: Max Reitz
Reviewed-by: Kevin Wolf
---
block/block-backend.c | 13 +
blockdev.c| 11 ---
include/sysemu/blockdev.h | 1 -
stubs/Makefile.objs | 1 -
stubs/blockdev.c
Creating an anonymous BDS can't fail. Make that obvious.
Signed-off-by: Markus Armbruster
Reviewed-by: Max Reitz
Reviewed-by: Benoît Canet
Reviewed-by: Kevin Wolf
---
block.c | 28 +++-
block/iscsi.c | 2 +-
block/vvfat.c | 2 +-
blockd
A block device consists of a frontend device model and a backend.
A block backend has a tree of block drivers doing the actual work.
The tree is managed by the block layer.
We currently use a single abstraction BlockDriverState both for tree
nodes and the backend as a whole. Drawbacks:
* Its AP
My last attempt got bogged down because I tried to do a reasonably
complete job, and the complexity proved more than I could handle with
the limited amount of uninterrupted time available. This time, I'm
cutting BlockBackend off with an axe, leaving most of the work for
later.
Done in this series
Signed-off-by: Markus Armbruster
Reviewed-by: Benoît Canet
Reviewed-by: Max Reitz
Reviewed-by: Kevin Wolf
---
block-migration.c | 30 +++---
block.c | 9 -
blockdev.c| 31 +--
include/block/block.h | 2
Make the BlockBackend own the DriveInfo. Change blockdev_init() to
return the BlockBackend instead of the DriveInfo.
Signed-off-by: Markus Armbruster
---
block.c | 2 --
block/block-backend.c | 38 ++
blockdev.c| 69
BlockBackend's name space is separate only to keep the initial patches
simple. Time to merge the two.
Retain bdrv_find() and bdrv_get_device_name() for now, to keep this
series manageable.
Signed-off-by: Markus Armbruster
---
block.c | 48 -
Commit 12c5674 turned it into a pointer to member blk.conf.
Signed-off-by: Markus Armbruster
Reviewed-by: Benoît Canet
Reviewed-by: Max Reitz
Reviewed-by: Kevin Wolf
---
hw/block/virtio-blk.c | 28 ++--
include/hw/virtio/virtio-blk.h | 1 -
2 files changed, 1
The patch is big, but all it really does is replacing
dinfo->bdrv
by
blk_bs(blk_by_legacy_dinfo(dinfo))
The replacement is repetitive, but the conversion of device models to
BlockBackend is imminent, and will shorten it to just
blk_legacy_dinfo(dinfo).
Line wrapping muddies the waters
Convenience function blk_new_with_bs() creates a BlockBackend with its
BlockDriverState. Callers have to unref both. The commit after next
will relieve them of the need to unref the BlockDriverState.
Complication: due to the silly way drive_del works, we need a way to
hide a BlockBackend, just l
Doesn't make a difference just yet, but it's the right thing to do.
Signed-off-by: Markus Armbruster
Reviewed-by: Benoît Canet
Reviewed-by: Kevin Wolf
---
block/block-backend.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/block/block-backend.c b/block/block-backend.c
index bdcbac6..d0
On BlockBackend destruction, unref its BlockDriverState. Replaces the
callers' unrefs.
This turns the pointer from BlockBackend to BlockDriverState into a
strong reference, managed with bdrv_ref() / bdrv_unref(). The
back-pointer remains weak.
Signed-off-by: Markus Armbruster
Reviewed-by: Max
Much more command code needs conversion. I start with this one
because it's using bdrv_dev_* functions, which I'm about to lift into
BlockBackend.
While there, give bdrv_query_info() internal linkage.
Signed-off-by: Markus Armbruster
Reviewed-by: Benoît Canet
Reviewed-by: Max Reitz
Reviewed-b
device_name[] can become non-empty only in bdrv_new_root() and
bdrv_move_feature_fields(). The latter is used only to undo damage
done by bdrv_swap(). The former is called only by blk_new_with_bs().
Therefore, when a BlockDriverState's device_name[] is non-empty, then
it's been created with a Blo
I'll use it with block backends shortly, and the name is going to fit
badly there. It's a block layer thing anyway, not just a block driver
thing.
Signed-off-by: Markus Armbruster
---
block.c | 30 +++---
block/archipelago.c | 8
blo
I'll use BlockDriverAIOCB with block backends shortly, and the name is
going to fit badly there. It's a block layer thing anyway, not just a
block driver thing.
Signed-off-by: Markus Armbruster
---
block-migration.c | 2 +-
block.c | 124 ++---
Signed-off-by: Markus Armbruster
Reviewed-by: Benoît Canet
Reviewed-by: Max Reitz
Reviewed-by: Kevin Wolf
---
block/block-backend.c | 1 -
blockdev.c| 3 +--
include/sysemu/blockdev.h | 1 -
3 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/block/block-backend.c
Add a BlockBackend member to TrimAIOCB, so ide_issue_trim_cb() can use
blk_aio_discard() instead of bdrv_aio_discard().
Signed-off-by: Markus Armbruster
Reviewed-by: Max Reitz
Reviewed-by: Kevin Wolf
---
hw/ide/core.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw
Signed-off-by: Markus Armbruster
Reviewed-by: Benoît Canet
Reviewed-by: Max Reitz
Reviewed-by: Kevin Wolf
---
include/hw/isa/pc87312.h | 3 ---
1 file changed, 3 deletions(-)
diff --git a/include/hw/isa/pc87312.h b/include/hw/isa/pc87312.h
index befc8bd..bf74470 100644
--- a/include/hw/isa/pc
Move device model attachment / detachment and the BlockDevOps device
model callbacks and their wrappers from BlockDriverState to
BlockBackend.
Wrapper calls in block.c change from
bdrv_dev_FOO_cb(bs, ...)
to
if (bs->blk) {
bdrv_dev_FOO_cb(bs->blk, ...);
}
No change, because
Much more command code needs conversion. I'm converting these now
because they're using bdrv_dev_* functions, which I'm about to lift
into BlockBackend.
Signed-off-by: Markus Armbruster
Reviewed-by: Benoît Canet
Reviewed-by: Max Reitz
Reviewed-by: Kevin Wolf
---
blockdev.c | 20 -
blockdev_init() always creates a DriveInfo, but only drive_new() fills
it in. qmp_blockdev_add() leaves it blank. This results in a drive
with type = IF_IDE, bus = 0, unit = 0. Screwed up in commit ee13ed1c.
Board initialization code looking for IDE drive (0,0) can pick up one
of these bogus dr
This series adds a field corresponding to the "corrupt" flag to
ImageInfoSpecificQCow2. This breaks several qemu-iotests which directly
invoke qemu-img info instead of using _img_info. Patch 1 tries to
minimize the necessary output fixes in patch 2 by replacing several
occurrences of direct qemu-im
The "corrupt" entry in the format-specific information section should be
"true".
Signed-off-by: Max Reitz
---
tests/qemu-iotests/060 | 3 +++
tests/qemu-iotests/060.out | 9 +
2 files changed, 12 insertions(+)
diff --git a/tests/qemu-iotests/060 b/tests/qemu-iotests/060
index 235556
Just like lazy-refcounts, this field will be present iff the qcow2
compat level is 1.1 (or probably any future revision).
As expected, this breaks some tests due to the new field present in
qemu-img info output; so fix their output accordingly.
Suggested-by: Eric Blake
Signed-off-by: Max Reitz
On 09/30/2014 01:31 PM, Max Reitz wrote:
> qemu-img info should only be used directly if the format-specific
> information or the name of the format is relevant (some tests explicitly
> test format-specific information; test 082 uses qcow2-specific settings
> to test the qemu-img interface); otherw
On 09/30/2014 01:31 PM, Max Reitz wrote:
> Just like lazy-refcounts, this field will be present iff the qcow2
> compat level is 1.1 (or probably any future revision).
>
> As expected, this breaks some tests due to the new field present in
> qemu-img info output; so fix their output accordingly.
>
On 09/30/2014 01:31 PM, Max Reitz wrote:
> The "corrupt" entry in the format-specific information section should be
> "true".
>
> Signed-off-by: Max Reitz
> ---
> tests/qemu-iotests/060 | 3 +++
> tests/qemu-iotests/060.out | 9 +
> 2 files changed, 12 insertions(+)
>
Reviewed-by:
qemu-img info should only be used directly if the format-specific
information or the name of the format is relevant (some tests explicitly
test format-specific information; test 082 uses qcow2-specific settings
to test the qemu-img interface); otherwise, tests should always use
_img_info instead.
On Tuesday, September 30, 2014 01:44:48 PM Al Patel wrote:
> Hi:
>
> I am running qemu-kvm version 1.0
>
> ($kvm -version
> QEMU emulator version 1.0 (qemu-kvm-1.0), Copyright (c) 2003-2008 Fabrice
> Bellard)
>
> When I start a VM with 4 vcpus, I see about 8 threads. (the thread count
> varies .
Which allows specification of absolute/relative,
up/down and console parameters.
Suggested by Gerd Hoffman.
Signed-off-by: Marcelo Tosatti
---
qapi-schema.json | 17 +
qmp-commands.hx | 63
++
ui/input.c | 37
On 09/30/2014 03:10 PM, Marcelo Tosatti wrote:
>
> Which allows specification of absolute/relative,
> up/down and console parameters.
>
> Suggested by Gerd Hoffman.
>
> Signed-off-by: Marcelo Tosatti
>
> ---
> qapi-schema.json | 17 +
> qmp-commands.hx | 63
> +++
From: Fabian Aggeler
Make arm_current_pl() return PL3 for secure PL1 and monitor mode.
Increase MMU modes since mmu_index is directly infered from arm_
current_pl(). Changes assertion in arm_el_is_aa64() to allow EL3.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cp
From: Sergey Fedorov
...from non-secure state.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Greg Bellows
---
target-arm/helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index
From: Fabian Aggeler
arm_is_secure() function allows to determine CPU security state
if the CPU implements Security Extensions/EL3.
arm_is_secure_below_el3() returns true if CPU is in secure state
below EL3.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellow
From: Fabian Aggeler
Increasing banked_r13 and banked_r14 to store LR_mon and SP_mon (bank
index 7).
Signed-off-by: Fabian Aggeler
Reviewed-by: Edgar E. Iglesias
Signed-off-by: Greg Bellows
---
target-arm/cpu.h | 4 ++--
target-arm/machine.c | 4 ++--
2 files changed, 4 insertions(+), 4
From: Fabian Aggeler
Define a new ARM CP register info list for the ARMv7 Security Extension
feature. Register that list only for ARM cores with Security Extension/EL3
support. Moving Aarch32 SCR into Security Extension register group.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Renamed the arm_current_pl CPU function to more accurately represent that it
returns the ARMv8 EL rather than ARMv7 PL.
Signed-off-by: Greg Bellows
---
target-arm/cpu.h | 18 +-
target-arm/helper-a64.c| 6 +++---
target-arm/helper.c| 22 +++-
Version 5 of the ARM processor security extension (TrustZone) support.
This patchset includes changes to support the processor security extensions
on ARMv7 aarch32 with hooks for later enabling v8 aarch64/32.
Summary of changes from v4 -> v5:
- Renamed arm_current_pl to arm_current_el
- Added bank
From: Fabian Aggeler
This patch extends arm_excp_unmasked() according to ARM ARMv7 and
ARM ARMv8 (all EL running in Aarch32) and adds comments.
If EL3 is using Aarch64 IRQ/FIQ masking is ignored in
all exception levels other than EL3 if SCR.{FIQ|IRQ} is
set to 1 (routed to EL3).
Signed-off-by:
From: Fabian Aggeler
Implements SMC instruction in Aarch32 using the A32 syndrome. When executing
SMC instruction from monitor CPU mode SCR.NS bit is reset.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
--
v4 -> v5
- Merge pre_smc upstream ch
From: Fabian Aggeler
Prepare ARMCPRegInfo to support specifying two fieldoffsets per
register definition. This will allow us to keep one register
definition for banked registers (different offsets for secure/
non-secure world).
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
From: Fabian Aggeler
Adds a dedicated function for IRQ and FIQ exceptions to determine
target_el and mode (Aarch32) according to tables in ARM ARMv8 and
ARM ARM v7.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
--
v4 -> v5
- Simplify target EL function including removal of
From: Sergey Fedorov
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 5be258b..f7148d1 100644
--- a/targe
From: Fabian Aggeler
Implements NSACR register with corresponding read/write functions
for ARMv7 and ARMv8.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
--
v4 -> v5
- Changed to use renamed arm_current_el()
---
target-arm/cpu.h| 6
From: Sergey Fedorov
This patch is based on idea found in patch at
git://github.com/jowinter/qemu-trustzone.git
f3d955c6c0ed8c46bc0eb10b634201032a651dd2 by
Johannes Winter .
This flag prevents QEMU from executing TCG code generated for other CPU
security state. It also allows to generate differe
From: Fabian Aggeler
bits when modifying CPSR.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
v3 -> v4
- Fixed up conditions for ignoring CPSR.A/F updates by isolating to v7 and
checking for the existence of EL3 and non-existence of EL2.
---
target-arm/helper.c |
From: Fabian Aggeler
Prepare for cp register banking by inserting every cp register twice,
once for secure world and once for non-secure world.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
--
v4 -> v5
- Added use of ARM CP secure/non-secure bank flags during register proc
From: Fabian Aggeler
Implements SCTLR_EL3 and uses secure/non-secure instance when
needed.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
hw/arm/pxa2xx.c| 2 +-
target-arm/cpu.c | 5 +--
target-arm/cpu.h | 13 +++-
target-arm/helper.c| 85 +
From: Fabian Aggeler
If EL3 is in Aarch32 state certain cp registers are banked (secure and
non-secure instance). When reading or writing to coprocessor registers
the following macros can be used.
- A32_BANKED macros are used for choosing the banked register based on provided
input security ar
From: Fabian Aggeler
Rename CSSELR (cache size selection register) and add secure
instance (Aarch32).
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
--
v4 -> v5
- Changed to use the CCSIDR cpreg bank flag to select the csselr bank instead
of the A32_BANKED macro. This m
From: Fabian Aggeler
Add TTBR0 and maps secure/non-secure instance of ttbr0 and ttbr1
accordingly (translation table base register).
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 21 +--
target-arm/helper.c | 58 +++
From: Fabian Aggeler
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
PAR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
-
v3 -> v4
- Fix par union/structure definition
---
target-arm/cpu.h| 10 +-
t
From: Fabian Aggeler
SCR.{IRQ/FIQ} bits allow to route IRQ/FIQ exceptions to monitor CPU
mode. When taking IRQ exception to monitor mode FIQ exception is
additionally masked.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/helper.c | 9 +
From: Fabian Aggeler
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
DACR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
hw/arm/pxa2xx.c | 2 +-
target-arm/cpu.h| 13 +++--
target-arm/helper.c | 19
From: Fabian Aggeler
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
VBAR has a secure and a non-secure instance, which are mapped to
VBAR_EL1 and VBAR_EL3.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
v3 -> v4
- Fix vbar union/structure defini
From: Fabian Aggeler
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
IFAR and DFAR have a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
-
v3 -> v4
- Revert to array-based notation of far_el in combination with v7
From: Fabian Aggeler
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
DFSR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
v3 -> v4
- Reverted esr/dfsr back to array-based notation as a union with v7 naming.
-
From: Fabian Aggeler
Use MVBAR register as exception vector base address for
exceptions taken to CPU monitor mode.
Signed-off-by: Sergey Fedorov
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 15 +--
2 files changed
Added the ability to print the scr register like can be done with the cpsr.
Signed-off-by: Greg Bellows
---
gdb-xml/arm-core.xml | 1 +
target-arm/cpu.c | 2 +-
target-arm/cpu.h | 2 ++
target-arm/gdbstub.c | 3 +++
target-arm/helper.c | 5 +
5 files changed, 12 insertions(+), 1 del
From: Fabian Aggeler
Since TTBCR is banked we will bank c2_mask and c2_base_mask too. This
avoids recalculating them on switches from secure to non-secure world.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
--
v4 -> v5
- Changed c2_mask updates to use the TTBCR cpreg bank
From: Fabian Aggeler
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
FCSEIDR, CONTEXTIDR, TPIDRURW, TPIDRURO and TPIDRPRW have a secure
and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
--
v3 -> v4
- Fix tpidrprw mapping
---
t
Added CP register info entries for the ARMv7 MAIR0/1 secure banks.
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 1 +
target-arm/helper.c | 6 --
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 1fa9e0d..7a8eaef 100644
--- a/tar
Quoting Alexander Graf (2014-08-26 06:36:57)
> On 19.08.14 02:21, Michael Roth wrote:
> > From: Mike Day
> >
> > Signed-off-by: Mike Day
> > Signed-off-by: Michael Roth
> > ---
> > hw/ppc/spapr_pci.c | 119
> > +
> > include/hw/ppc/spapr.h |
From: Fabian Aggeler
Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.c | 4
1 file changed, 4 insertions(+)
diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index ea2169b..2a0eeb3 10064
From: Fabian Aggeler
When EL3 is running in Aarch32 (or ARMv7 with Security Extensions)
IFSR has a secure and a non-secure instance.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
---
target-arm/cpu.h| 10 +-
target-arm/helper.c | 9 +
2 files changed, 14 inser
From: Fabian Aggeler
Adds TCR_EL3 system register and makes existing TTBCR banked. Adjust
translation functions to use TCR/TTBCR instance depending on CPU state.
Signed-off-by: Fabian Aggeler
Signed-off-by: Greg Bellows
--
v4 -> v5
- Changed c2_mask updates to use the TTBCR cpreg bank
Il 30/09/2014 20:26, Eduardo Habkost ha scritto:
> Other test code will use the function.
>
> Signed-off-by: Eduardo Habkost
> ---
> tests/Makefile | 1 +
> tests/coroutine-stub.c | 13 +
> tests/test-vmstate.c | 11 ---
> 3 files changed, 14 insertions(+), 11 dele
Il 30/09/2014 20:26, Eduardo Habkost ha scritto:
> Reasoning for each object file included in the test binary:
> * qom/cpu.o - for TYPE_CPU. Dependencies:
>* qom/qom-qobject.o
> * qom/qdev.o - for TYPE_DEVICE. Dependencies:
>* qom/container.o
>* vmstate.o. Dependencies:
> * qemu-
On Tue, Sep 30, 2014 at 04:49:14PM -0500, Greg Bellows wrote:
> From: Fabian Aggeler
>
> arm_is_secure() function allows to determine CPU security state
> if the CPU implements Security Extensions/EL3.
> arm_is_secure_below_el3() returns true if CPU is in secure state
> below EL3.
Hi Greg,
>
>
On Tue, Sep 30, 2014 at 04:49:16PM -0500, Greg Bellows wrote:
> Renamed the arm_current_pl CPU function to more accurately represent that it
> returns the ARMv8 EL rather than ARMv7 PL.
>
> Signed-off-by: Greg Bellows
> ---
> target-arm/cpu.h | 18 +-
> target-arm/helpe
On Tue, Sep 30, 2014 at 04:49:34PM -0500, Greg Bellows wrote:
> From: Fabian Aggeler
>
> Adds TCR_EL3 system register and makes existing TTBCR banked. Adjust
> translation functions to use TCR/TTBCR instance depending on CPU state.
>
> Signed-off-by: Fabian Aggeler
> Signed-off-by: Greg Bellows
On 09/30/2014 03:38 AM, Markus Armbruster wrote:
John Snow writes:
Instead of duplicating the logic for the if_ide
(bus,unit) mappings, rely on the blockdev layer
for managing those mappings for us, and use the
drive_get_by_index call instead.
This allows ide_drive_get to work for AHCI HBAs
On 30.09.2014 14:49, Greg Bellows wrote:
> From: Fabian Aggeler
>
> Make arm_current_pl() return PL3 for secure PL1 and monitor mode.
> Increase MMU modes since mmu_index is directly infered from arm_
> current_pl(). Changes assertion in arm_el_is_aa64() to allow EL3.
arm_current_pl() is renamed
> Subject: Re: [Qemu-devel] [PATCH v4 1/5] qdev: add description field in
> PropertyInfo struct
>
> Il 30/09/2014 16:01, Michael S. Tsirkin ha scritto:
> > > No, as Markus said "06.0" is 48, "06.1" is 49, etc.
> >
> > I see. So in fact the help text I suggested is wrong.
> > At least for HMP I wou
> Subject: Re: [Qemu-devel] [PATCH v4 2/3] pcie: add check for ari capability of
> pcie devices
>
> On Tue, Sep 30, 2014 at 09:38:51PM +0800, Gonglei wrote:
> > > Subject: Re: [Qemu-devel] [PATCH v4 2/3] pcie: add check for ari
> > > capability of
> > > pcie devices
> > >
> > > On Tue, Sep 30, 20
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