On Mon, 16 Dec 2013 16:26:55 -0200
Eduardo Habkost wrote:
> On Mon, Dec 16, 2013 at 04:01:05PM +0100, Igor Mammedov wrote:
> > On Sun, 15 Dec 2013 23:50:47 +0100
> > Andreas Färber wrote:
> >
> > > Am 27.11.2013 23:28, schrieb Igor Mammedov:
> > > > Igor Mammedov (16):
> > > > target-i386: cl
On Mon, 06 Jan 2014 21:53:50 -0800
"H. Peter Anvin" wrote:
> On 03/25/2013 01:56 PM, Eduardo Habkost wrote:
> >
> >>
> >> It needs to be possible to fix bugs
> >
> > It is possible to fix them today: just write a compat function or add a
> > global variable that is handled by cpu_x86_init()
"Kirill A. Shutemov" writes:
> Aneesh Kumar K.V wrote:
>> "Kirill A. Shutemov" writes:
>>
>> > Kirill A. Shutemov wrote:
>> >> Currently we have few issues with P9_STATS_GEN:
>> >>
>> >> - We don't try to read st_gen anything except files or directories, but
>> >>still set P9_STATS_GEN bi
"Michael S. Tsirkin" writes:
> On Tue, Dec 24, 2013 at 06:04:12PM +0100, Andreas Färber wrote:
>> From: Markus Armbruster
>>
>> In an ideal world, machines can be built by wiring devices together
>> with configuration, not code. Unfortunately, that's not the world we
>> live in right now. We
Stefan Hajnoczi writes:
> On Tue, Dec 31, 2013 at 01:19:02AM +0100, Andreas Färber wrote:
>> Am 30.12.2013 09:46, schrieb Kewei Yu:
>> > When we disabling vnc from "./configure", the qemu can't use the vnc
>> > option.
>> > So qtest can't use the "vnc -none ", otherwise "make check" will hang.
>
Am 07.01.2014 11:35, schrieb Markus Armbruster:
> Stefan Hajnoczi writes:
>> On Tue, Dec 31, 2013 at 01:19:02AM +0100, Andreas Färber wrote:
>>> Am 30.12.2013 09:46, schrieb Kewei Yu:
diff --git a/tests/fdc-test.c b/tests/fdc-test.c
index 38b5b17..80dbdfb 100644
--- a/tests/fdc-test
comments below
On 01/05/14 08:27, Qiao Nuohan wrote:
> the functions are used to write header of kdump-compressed format to vmcore.
> Header of kdump-compressed format includes:
> 1. common header: DiskDumpHeader32 / DiskDumpHeader64
> 2. sub header: KdumpSubHeader32 / KdumpSubHeader64
> 3. extra
Am 07.01.2014 12:38, schrieb Laszlo Ersek:
> Also... is it OK to write these fields to the file in host native byte
> order? What happens if an i686 / x86_64 target is emulated on a BE host?
For the target-s390x implementation Alex required to take care of
endianness for the s390x-on-x86 case, so
Am 07.01.2014 11:28, schrieb Markus Armbruster:
> "Michael S. Tsirkin" writes:
>
>> On Tue, Dec 24, 2013 at 06:04:12PM +0100, Andreas Färber wrote:
>>> From: Markus Armbruster
>>>
>>> In an ideal world, machines can be built by wiring devices together
>>> with configuration, not code. Unfortuna
Michael Roth writes:
> Quoting Markus Armbruster (2013-12-17 01:20:16)
>> [Cc: Anthony, Mike for QAPI schema expertise]
>>
>> Luiz Capitulino writes:
>>
>> > On Tue, 10 Dec 2013 19:15:05 +0100
>> > Paolo Bonzini wrote:
>> >
>> >> -BEGIN PGP SIGNED MESSAGE-
>> >> Hash: SHA1
>> >>
>> >
Ping?
Markus Armbruster writes:
> [Licensing problem, cc: Anthony]
>
> Kevin Wolf writes:
>
>> Am 13.12.2013 um 14:31 hat Eric Blake geschrieben:
>>> On 11/12/2013 06:44 PM, Wenchao Xia wrote:
>>> > +++ b/scripts/qapi-event.py
>>> > @@ -0,0 +1,355 @@
>>> > +#
>>> > +# QAPI event generator
>>> >
Am 16.12.2013 10:33, schrieb Peter Maydell:
> Anyway, I don't actively object to this series. I just think
> Anthony's going in the wrong direction which is why I haven't
> been particularly eager to actively mark it as reviewed-by me
> either...
Sorry for not taking the time to reply to these con
On Mon, Jan 06, 2014 at 09:53:37PM +0100, Paolo Bonzini wrote:
> Il 06/01/2014 19:00, Andreas Färber ha scritto:
> > Am 06.01.2014 16:39, schrieb Anthony Liguori:
> >> We already have accel=xen. I'm echoing Peter's suggestion of having the
> >> ability to compile out accel=tcg.
> >
> > Didn't you
On 7 January 2014 12:33, Andreas Färber wrote:
> Am 16.12.2013 10:33, schrieb Peter Maydell:
>> Anyway, I don't actively object to this series. I just think
>> Anthony's going in the wrong direction which is why I haven't
>> been particularly eager to actively mark it as reviewed-by me
>> either..
Il 07/01/2014 13:00, Markus Armbruster ha scritto:
>> >
>> > Is dumping static properties based on class name sufficient, or do we
>> > need introspection for dynamic properties as well? (or are those not
>> > exposed outside of qom-set?)
>
> Can't say whether introspection limited to static prope
Cc: qemu-triv...@nongnu.org
Signed-off-by: Namhyung Kim
---
docs/qmp/qmp-events.txt |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/docs/qmp/qmp-events.txt b/docs/qmp/qmp-events.txt
index 6b87e97..a378c87 100644
--- a/docs/qmp/qmp-events.txt
+++ b/docs/qmp/qmp-events.txt
@@
Am 07.01.2014 13:43, schrieb Peter Maydell:
> On 7 January 2014 12:33, Andreas Färber wrote:
>> Am 16.12.2013 10:33, schrieb Peter Maydell:
>>> Anyway, I don't actively object to this series. I just think
>>> Anthony's going in the wrong direction which is why I haven't
>>> been particularly eager
On Tue, Jan 7, 2014 at 10:43 PM, Peter Maydell wrote:
> On 7 January 2014 12:33, Andreas Färber wrote:
>> Am 16.12.2013 10:33, schrieb Peter Maydell:
>>> Anyway, I don't actively object to this series. I just think
>>> Anthony's going in the wrong direction which is why I haven't
>>> been particu
On Mon, 6 Jan 2014, Wei Liu wrote:
> On Mon, Jan 06, 2014 at 07:12:07PM +0100, Andreas Färber wrote:
> > Am 06.01.2014 16:12, schrieb Wei Liu:
> > > On Mon, Jan 06, 2014 at 01:30:20PM +, Peter Maydell wrote:
> > >> On 6 January 2014 12:54, Wei Liu wrote:
> > >>> In fact I've already hacked a p
On 12/25/2013 02:43 AM, Michael S. Tsirkin wrote:
> On Wed, Dec 25, 2013 at 01:15:29AM +1100, Alexey Kardashevskiy wrote:
>> On 12/24/2013 08:40 PM, Michael S. Tsirkin wrote:
>>> On Tue, Dec 24, 2013 at 02:09:07PM +1100, Alexey Kardashevskiy wrote:
On 12/24/2013 03:24 AM, Michael S. Tsirkin wr
On Mon, 6 Jan 2014, Peter Maydell wrote:
> On 6 January 2014 17:34, Stefano Stabellini
> wrote:
> > On Mon, 6 Jan 2014, Peter Maydell wrote:
> >> However I don't think we can have a qemu-system-null
> >> (regardless of use cases) until/unless we get rid of
> >> all the things which are compile-tim
Il 07/01/2014 13:34, Wei Liu ha scritto:
> On Mon, Jan 06, 2014 at 09:53:37PM +0100, Paolo Bonzini wrote:
>> Il 06/01/2014 19:00, Andreas Färber ha scritto:
>>> Am 06.01.2014 16:39, schrieb Anthony Liguori:
We already have accel=xen. I'm echoing Peter's suggestion of having the
ability t
On 7 January 2014 13:26, Stefano Stabellini
wrote:
> On Mon, 6 Jan 2014, Peter Maydell wrote:
>> The identifiers poisoned by include/qemu/poison.h are
>> an initial but not complete list. Host and target
>> endianness is a particularly obvious one, as is the
>> size of a target long. You may not u
On Tue, Jan 07, 2014 at 02:32:38PM +0100, Paolo Bonzini wrote:
> Il 07/01/2014 13:34, Wei Liu ha scritto:
> > On Mon, Jan 06, 2014 at 09:53:37PM +0100, Paolo Bonzini wrote:
> >> Il 06/01/2014 19:00, Andreas Färber ha scritto:
> >>> Am 06.01.2014 16:39, schrieb Anthony Liguori:
> We already hav
Juan Quintela wrote:
> Hi
>
> First of all, poll told to move the call earlier.
>
> 9:00 EST (15:00 CET or 6:00 Pacific)
>
>
> Please, send any topic that you are interested in covering.
As there are no topics, we leave the call for 2014-01-21
Happy hacking.
Il 07/01/2014 14:26, Stefano Stabellini ha scritto:
> > The identifiers poisoned by include/qemu/poison.h are
> > an initial but not complete list. Host and target
> > endianness is a particularly obvious one, as is the
> > size of a target long. You may not use these things
> > in your Xen devices
Namhyung Kim writes:
> Cc: qemu-triv...@nongnu.org
> Signed-off-by: Namhyung Kim
> ---
> docs/qmp/qmp-events.txt |2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/docs/qmp/qmp-events.txt b/docs/qmp/qmp-events.txt
> index 6b87e97..a378c87 100644
> --- a/docs/qmp/qmp-eve
Peter Maydell writes:
> On 7 January 2014 12:33, Andreas Färber wrote:
>> Am 16.12.2013 10:33, schrieb Peter Maydell:
>>> Anyway, I don't actively object to this series. I just think
>>> Anthony's going in the wrong direction which is why I haven't
>>> been particularly eager to actively mark it
On Tue, 7 Jan 2014, Paolo Bonzini wrote:
> Il 07/01/2014 14:26, Stefano Stabellini ha scritto:
> > > The identifiers poisoned by include/qemu/poison.h are
> > > an initial but not complete list. Host and target
> > > endianness is a particularly obvious one, as is the
> > > size of a target long. Y
On Tue, Jan 07, 2014 at 02:50:12PM +0100, Paolo Bonzini wrote:
> Il 07/01/2014 14:26, Stefano Stabellini ha scritto:
> > > The identifiers poisoned by include/qemu/poison.h are
> > > an initial but not complete list. Host and target
> > > endianness is a particularly obvious one, as is the
> > > si
Il 06/01/2014 07:05, Kewei Yu ha scritto:
> When we disable vnc from "./configure", QEMU can't use the vnc option.
> So qtest can't use the "vnc -none ", otherwise "make check" fails.
> If QEMU uses "-display none", "-vnc none" is excrescent, So we just need to
> drop it.
>
> Signed-off-by: Kewei
Il 07/01/2014 15:38, Wei Liu ha scritto:
> On Tue, Jan 07, 2014 at 02:50:12PM +0100, Paolo Bonzini wrote:
>> Il 07/01/2014 14:26, Stefano Stabellini ha scritto:
The identifiers poisoned by include/qemu/poison.h are
an initial but not complete list. Host and target
endianness is a par
Il 05/01/2014 16:04, Miki Mishael ha scritto:
> Support for pci-serial-2x and pci-serial-4x added to inf file.
> Standard Windows driver mf.sys used to split single function
> device into per-port nodes.
>
> Signed-off-by: Miki Mishael
> Signed-off-by: Dmitry Fleytman
> ---
> docs/qemupciserial
Il 02/01/2014 17:15, Richard W.M. Jones ha scritto:
>
> My (possibly weak) understanding of the upstream qemu code is that
> unmap/discard/trim is not supported in qcow2. It is only supported in
> raw files when using a POSIX-like host OS which has either of:
>
> - block devices supporting BLKD
Paolo Bonzini writes:
> Il 21/12/2013 11:42, Markus Armbruster ha scritto:
>> Suggest to add: ", killing migration."
>
> Not good. But perhaps we can give a reason for this 2.0 thing.
>
> It is certainly nice to schedule incompatible changes for obscure
> machine types every 2 years.
>
>> Which
On 7 January 2014 13:50, Paolo Bonzini wrote:
> So let's call things by their name and add qemu-system-xenpv that covers
> both x86 and ARM and anything else in the future.
How is this going to work? Do you define a fake architecture
name "xenpv" ? I guess we'll see what the patches look like...
comments below
On 01/05/14 08:27, Qiao Nuohan wrote:
> DataCache is used to store data temporarily, then the data will be written to
> vmcore. These functions will be called later when writing data of page to
> vmcore.
>
> Signed-off-by: Qiao Nuohan
> ---
> dump.c| 52
> +
Il 07/01/2014 16:11, Peter Maydell ha scritto:
>> > So let's call things by their name and add qemu-system-xenpv that covers
>> > both x86 and ARM and anything else in the future.
> How is this going to work? Do you define a fake architecture
> name "xenpv" ?
Yes, one that aborts if a CPU is creat
comments below
On 01/05/14 08:27, Qiao Nuohan wrote:
> functions are used to write 1st and 2nd dump_bitmap of kdump-compressed
> format,
> which is used to indicate whether the corresponded page is existed in vmcore.
> 1st and 2nd dump_bitmap are same, because dump level is specified to 1 here.
>
Signed-off-by: Orit Wasserman
---
arch_init.c | 4
migration.c | 10 +-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch_init.c b/arch_init.c
index 5c55c68..e52c9ba 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -176,6 +176,10 @@ static struct {
int64_t xbzrle_c
Signed-off-by: Orit Wasserman
---
arch_init.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch_init.c b/arch_init.c
index e0acbc5..5c55c68 100644
--- a/arch_init.c
+++ b/arch_init.c
@@ -587,6 +587,9 @@ static void migration_end(void)
g_free(XBZRLE.current_buf);
g_free
The QEMU emulation models for Power7 and Power8 are still missing some
of the base instructions that were introduced in Power ISA 2.06 and
even a few that were introduced prior to that.
This patch series gets these models caught up with respect to the
base 2.06 ISA. That is, the Book I and Book I
This patch addes the Unsigned Divide Word Extended instructions
which were introduced in Power ISA 2.06B.
Signed-off-by: Tom Musta
---
V2: Eliminating extraneous code in the overflow case per comments
from Richard Henderson. Fixed corner case bug in divweu (check
for (RA) >= (RB)).
V4: Using ne
This patch adds the Divide Doubleword Extended Unsigned
instructions. This instruction requires dividing a 128-bit
value by a 64 bit value. Since 128 bit integer division is
not supported in TCG, a helper is used. An architecture
independent 128-bit division routine is added to host-utils.
Sign
This patch adds a flag for the Divide Extended instructions that
were introduced in Power ISA V2.06B. The flag is added to the
Power7 and Power8 models.
Signed-off-by: Tom Musta
---
V4: Split into new and separate patch. Added flag to Power7+
model.
target-ppc/cpu.h|5 -
t
This patch adds the Divide Doubleword Extended instructions.
The implementation builds on the unsigned helper provided in
the previous patch.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
---
V2: Updated to use the host-utils 128 bit divide.
V4: Using the newly addedd PPC2_DIVE_ISA206
This patch adds a flag for the floating point conversion instructions
introduced in Power ISA 2.06B.
Signed-off-by: Tom Musta
---
V4: Split single flag into multiple flags per discussion with
Alex Graf and Scott Wood. Added to Power7+ config.
target-ppc/cpu.h|5 -
target-pp
This patch adds the fcfids, fcfidu and fcfidus instructions which
were introduced in Power ISA 2.06B. A common macro is provided to
eliminate repetitious code, and the existing fcfid instruction is
refactored to use this macro.
Signed-off-by: Tom Musta
---
V4: Using the newly added PPC2_FP_CVT_I
From: Peter Maydell
Refactor the code in various functions which calculates rounding
increments given the current rounding mode, so that instead of a
set of nested if statements we have a simple switch statement.
This will give us a clean place to add the case for the new
tiesAway rounding mode.
This patch adds the byte and halfword variants of the Store Conditional
instructions. A common macro is introduced and the existing implementations
of stwcx. and stdcx. are refactored to use this macro.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
---
V2: Re-implemented gen_conditio
This patch adds the Floating Point Test for Divide instruction which
was introduced in Power ISA 2.06B.
Signed-off-by: Tom Musta
---
V4: Using the newly added PPC2_FP_TST_ISA206 flag. Modified helper
signature per Richard Henderson's review.
target-ppc/fpu_helper.c | 56 +
This patch adds a flag for Floating Point Test instructions that were
introduced in Power ISA V2.06B.
Signed-off-by: Tom Musta
---
V4: Split single flag into multiple flags per discussion with
Alex Graf and Scott Wood. Added flag to Power7+ model.
target-ppc/cpu.h|4 +++-
targe
This patch adds the Floating Point Test for Square Root instruction
which was introduced in Power ISA 2.06.
Signed-off-by: Tom Musta
---
V4: Using the newly added PPC2_FP_TST_ISA206 flag. Modified helper
signature per Richard Henderson's review.
target-ppc/fpu_helper.c | 31 +
This patch adds the Load Floating Point as Integer Word and
Zero Indexed (lfiwzx) instruction which was introduced in
Power ISA 2.06.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
---
V4: Using the PPC2_FP_CVT_ISA206 flag.
target-ppc/translate.c | 15 +++
1 files change
The frsqrtes instruction was introduced prior to ISA 2.06 and is
support on both the Power7 and Power8 processors. However, this
instruction is handled as illegal in the current QEMU emulation
machines. This patch enables the existing implemention of frsqrtes
in the P7 and P8 machines.
Signed-of
Eduardo Otubo writes:
> The following changes since commit 2a13f991123fa16841e6d94b02a9cc2c76d91725:
>
> seccomp: exit if seccomp_init() fails (2013-12-20 16:38:29 -0200)
>
> are available in the git repository at:
> git://github.com/otubo/qemu.git seccomp
It's been almost three weeks. What
If we have a C++ compiler available, link with it, because we might be
linking some C++ files in. This allows us to include C++ object files
in the QEMU binary proper.
Signed-off-by: Peter Maydell
---
rules.mak | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/rules.mak
This patch adds the four floating point to integer conversion instructions
introduced by Power ISA V2.06:
- Floating Convert to Integer Word Unsigned (fctiwu)
- Floating Convert to Integer Word Unsigned with Round Toward
Zero (fctiwuz)
- Floating Convert to Integer Doubleword Unsigned (f
Il 07/01/2014 13:43, Peter Maydell ha scritto:
> Sure. I think the right way to do that is to only allow
> them to plug in devices that are truly pluggable (ie which
> are on some pluggable bus like PCI or USB), rather than
> this way round, which is trying to blacklist devices rather
> than whitel
The fri* series of instructions was introduced prior to ISA 2.06 and
is supported on Power7 and Power8 hardware. However, the instruction
is still considered illegal in the P7 and P8 QEMU emulation models.
This patch enables these instructions for the P7 and P8 machines.
Also, the existing helper
Hi. This is a rebased and mildly cleaned up version of Claudio's
RFC patchset from last year to add libvixl to QEMU and use it
for A64 disassembly.
NOTE NOTE NOTE
* we now link with g++, not gcc (even if the target doesn't
happen to need the A64 disassembler, since it's a bit hard
to tell w
The A64 disassembler libvixl uses .cc as its suffix for
C++ source files, so add support for it (we already support
.cpp).
Signed-off-by: Peter Maydell
---
rules.mak | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/rules.mak b/rules.mak
index 49edb9b..cd9187e 100644
--- a
From: Claudio Fontana
Use libvixl to implement disassembly output in debug
logs for A64, for both AArch64 hosts and targets.
Signed-off-by: Claudio Fontana
[PMM:
* added support for target disassembly
* switched to custom QEMUDisassembler so the output format
matches what QEMU expects
* m
Il 07/01/2014 16:12, Markus Armbruster ha scritto:
> aarch64 akita info qtree crashes
> aarch64 borzoi info qtree crashes
> aarch64 spitz info qtree crashes
> aarch64 terrier info qtree crashes
> aarch64 tosain
Am 07.01.2014 um 15:41 hat Paolo Bonzini geschrieben:
> Il 06/01/2014 07:05, Kewei Yu ha scritto:
> > When we disable vnc from "./configure", QEMU can't use the vnc option.
> > So qtest can't use the "vnc -none ", otherwise "make check" fails.
> > If QEMU uses "-display none", "-vnc none" is excres
This patch adds the Bit Permute Doubleword (bpermd) instruction,
which was introduced in Power ISA 2.06 as part of the base 64-bit
architecture.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
---
V2: Addressing stylistic comments from Richard Henderson.
V4: Use newly added PPC2_PERM_IS
This patch addes the signed Divide Word Extended instructions
which were introduced in Power ISA 2.06B.
Signed-off-by: Tom Musta
---
V2: Eliminating extraneous code in the overflow case per comments
from Richard Henderson. Fixed corner case bug in divweu (check
for (RA) >= (RB)).
V4: Using newl
From: Peter Maydell
IEEE754-2008 specifies a new rounding mode:
"roundTiesToAway: the floating-point number nearest to the infinitely
precise result shall be delivered; if the two nearest floating-point
numbers bracketing an unrepresentable infinitely precise result are
equally near, the one wit
This patch adds the byte and halfword variants of the Load and
Reserve instructions. Since there is much commonality among
all forms of Load and Reserve, a macro is provided and the existing
implementations of lwarx and ldarx are refactoried to use this
macro.
Signed-off-by: Tom Musta
Reviewed-
Am 06.01.2014 um 14:17 hat Eric Blake geschrieben:
> On 01/05/2014 09:39 PM, Stefan Hajnoczi wrote:
> > Commit 9117b47717ad208b12786ce88eacb013f9b3dd1c ("qcow2: Change default
> > for new images to compat=1.1") changed the default qcow2 image format
> > version but forgot to update qemu-doc.texi an
This patch adds a flag for the atomic instructions introduced
in Power ISA V2.06B.
Signed-off-by: Tom Musta
---
V4: Split into new and separate patch. Added to Power7+ model.
target-ppc/cpu.h|5 -
target-ppc/translate_init.c |9 ++---
2 files changed, 10 insertions(
From: Peter Maydell
In preparation for adding conversions between float16 and float64,
factor out code currently done inline in the float16<=>float32
conversion functions into functions RoundAndPackFloat16 and
NormalizeFloat16Subnormal along the lines of the existing versions
for the other float
From: Peter Maydell
Our float32 to float16 conversion routine was generating the correct
numerical answers, but not always setting the right set of exception
flags. Fix this, mostly by rearranging the code to more closely
resemble RoundAndPackFloat*, and in particular:
* non-IEEE halfprec always
Paolo Bonzini writes:
> Il 07/01/2014 16:12, Markus Armbruster ha scritto:
>> aarch64 akita info qtree crashes
>> aarch64 borzoi info qtree crashes
>> aarch64 spitz info qtree crashes
>> aarch64 terrier info qtree crashes
>>
Hello,
would somebody mind committing this.
On 12/06/2013 06:48 PM, Richard Henderson wrote:
On 11/27/2013 08:50 PM, Sebastian Huber wrote:
Synchronize the program counter before the power down helper call
otherwise interrupts will return to the wrong context.
Signed-off-by: Sebastian Huber
This would allow a user to be able to refer to the device when using commands
like device_del.
Signed-off-by: Hani Benhabiles
---
qdev-monitor.c | 64 +-
1 file changed, 50 insertions(+), 14 deletions(-)
diff --git a/qdev-monitor.c b/qdev-
On 6 January 2014 11:30, Peter Maydell wrote:
> @@ -1946,7 +1947,34 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const
> ARMCPRegInfo *r,
> uint32_t *key = g_new(uint32_t, 1);
> ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
> int is64 = (r->type & ARM_CP_64BIT) ? 1 :
On 6 January 2014 11:30, Peter Maydell wrote:
> First target-arm pull request of the year; please pull.
...and first brown-paper-bag bug of the year: this
breaks booting of Linux when emulating ARMv7 32 bit
CPUs.
Please ignore this pull request. I'll fix things up
and resubmit. (I'm also plannin
Le 06/01/2014 20:18, André Hentschel a écrit :
From: André Hentschel
Cc: Riku Voipio
Signed-off-by: André Hentschel
Reviewed-by: Laurent Vivier
In preparation for adding conversions between float16 and float64,
factor out code currently done inline in the float16<=>float32
conversion functions into functions RoundAndPackFloat16 and
NormalizeFloat16Subnormal along the lines of the existing versions
for the other float types.
Note that we c
Our float32 to float16 conversion routine was generating the correct
numerical answers, but not always setting the right set of exception
flags. Fix this, mostly by rearranging the code to more closely
resemble RoundAndPackFloat*, and in particular:
* non-IEEE halfprec always raises Invalid for in
define_one_arm_cp_reg_with_opaque() has a set of nested loops which
insert a cpreg entry into the hashtable for each of the possible
opc/crn/crm values allowed by wildcard specifications. We're about
to add an extra loop to this nesting, so pull the core of the loop
(which adds a single entry to th
From: Tom Musta
This patch adds the float32_to_uint64() routine, which converts a
32-bit floating point number to an unsigned 64 bit number.
This contribution can be licensed under either the softfloat-2a or -2b
license.
Signed-off-by: Tom Musta
Reviewed-by: Peter Maydell
[PMM: removed harmle
Implement FMOV, ie non-converting moves between general purpose
registers and floating point registers. This is a subtype of
the floating point <-> integer instruction class.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 86
From: Alexander Graf
This patch adds emulation for the instruction group labeled
"Floating-point <-> fixed-point conversions" in the ARM ARM.
Namely this includes the instructions SCVTF, UCVTF, FCVTZS, FCVTZU
(scalar, fixed-point).
Signed-off-by: Alexander Graf
[WN: Commit message tweak, rebas
From: Will Newton
Make the VFP_CONV_FIX helpers a little more flexible in
preparation for the A64 uses. This requires two changes:
* use the correct softfloat conversion function based on itype
rather than always the int32 one; this is possible now that
softfloat provides int16 versions an
From: Tom Musta
The float64_to_uint64_round_to_zero routine is incorrect.
For example, the following test pattern:
46697351FF4AEC29 / 0x1.97351ff4aec29p+103
currently produces 8000 instead of .
This patch re-implements the routine to temporarily force the
round
Tidy up the get/set accessors for the fp state to add missing ones
and make them all inline in softfloat.h rather than some inline and
some not.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
fpu/softfloat.c | 15 ---
include/fpu/softfloat.h | 39 +++
From: Peter Crosthwaite
There is an inline duplication of the raw_read and raw_write function
bodies. Fix by just calling raw_read/raw_write instead.
Signed-off-by: Peter Crosthwaite
Reviewed-by: Peter Maydell
Message-id:
e69281b7e1462b346cb313cf0b89eedc0568125f.1388649290.git.peter.crosthwa.
From: Alexander Graf
Adds support for Load Register (literal), both normal
and SIMD/FP forms.
Signed-off-by: Alexander Graf
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 47
From: Will Newton
Use the helpers provided for getting the correct FPSR and FPCR
values for the signal context.
Signed-off-by: Will Newton
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
linux-user/signal.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
dif
From: Will Newton
ARMv8 requires support for converting 32 and 64bit floating point
values to signed and unsigned 16bit integers.
Signed-off-by: Will Newton
[PMM: updated not to incorrectly set Inexact for Invalid inputs]
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
fpu/so
In preparation for adding support for A64 load/store exclusive instructions,
widen the fields in the CPU state struct that deal with address and data values
for exclusives from 32 to 64 bits. Although in practice AArch64 and AArch32
exclusive accesses will be generally separate there are some odd t
From: Alexander Graf
When setting rounding modes we currently just hardcode the numeric values
for rounding modes in a big switch statement.
With AArch64 support coming, we will need to refer to these rounding modes
at different places throughout the code though, so let's better give them
names
On Tue, Jan 07, 2014 at 03:48:54PM +0100, Paolo Bonzini wrote:
> Il 02/01/2014 17:15, Richard W.M. Jones ha scritto:
> >
> > My (possibly weak) understanding of the upstream qemu code is that
> > unmap/discard/trim is not supported in qcow2. It is only supported in
> > raw files when using a POSI
From: Claudio Fontana
This adds decoding support for C3.6.24 FP conditional select.
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 45 -
1 file changed, 44 insertions(+),
From: Peter Crosthwaite
As per current QOM conventions.
Signed-off-by: Peter Crosthwaite
Message-id:
a1e31bd62e9709ffb9b3efc6c120f83f30b7a660.1388626249.git.peter.crosthwa...@xilinx.com
Signed-off-by: Peter Maydell
---
hw/char/cadence_uart.c | 2 ++
1 file changed, 2 insertions(+)
diff --gi
Il 07/01/2014 21:27, Richard W.M. Jones ha scritto:
> Not much more what I said in the original email (especially see the
> attached script which you can download from the bottom of this page:
> https://lists.gnu.org/archive/html/qemu-devel/2014-01/msg00084.html )
>
> Basically it tries to dd /dev
The previous placement could result in duplicate logging while
still processing interrupts.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
cpu-exec.c | 36 +++-
1 file changed, 19 insertions(+), 17 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec
The reg_ptr and offset_ptr outputs are universally unused.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target-i386/translate.c | 146 +++-
1 file changed, 69 insertions(+), 77 deletions(-)
diff --git a/target-i386/translate.c b/ta
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