The QEMU emulation models for Power7 and Power8 are still missing some
of the base instructions that were introduced in Power ISA 2.06 and
even a few that were introduced prior to that.
This patch series gets these models caught up with respect to the
base 2.06 ISA. That is, the Book I and Book II instructions for
the branch, fixed point and floating point units will be completed
with this series. Decimal floating point is not addressed in this
series, nor are the base ISA 2.07 changes for the Power8 model.
In some cases, existing instructions are re-implemented using common
macros, thus eliminating some redundant code. The patch series
eliminates almost half as much code as it adds.
Additionally, some bugs in the common floating point library (softfloat)
are fixed.
V2: Addressing comments from Richard Henderson. Fixed corner case bug
in divweu.
V3: Addressing comments from Peter Maydell. softloat changes have been
moved back to the VSX stage 3 patch series.
V4:
- Split the single flag (PPC2_ISA206) into multiple flags per request from
Alex Graf.
- Recoded divwe[u] instructions as a helper.
- Correct tcg-debug compilation errors.
- Corrected fcfid[u]s helpers to avoid double rounding.
- Corrected frin to use "nearest ties away" rounding mode instead of
"nearest ties to even".
- Updated (new) Power7+ model to include all newly added instruction flags.
- Assorted comments from Richard Henderson, Peter Maydell and Scott Wood.
Tom Musta (22):
target-ppc: Add ISA2.06 bpermd Instruction
target-ppc: Add Flag for ISA2.06 Divide Extended Instructions
target-ppc: Add ISA2.06 divdeu[o] Instructions
target-ppc: Add ISA2.06 divde[o] Instructions
target-ppc: Add ISA 2.06 divweu[o] Instructions
target-ppc: Add ISA 2.06 divwe[o] Instructions
target-ppc: Add Flag for ISA2.06 Atomic Instructions
target-ppc: Add ISA2.06 lbarx, lharx Instructions
target-ppc: Add ISA 2.06 stbcx. and sthcx. Instructions
target-ppc: Add Flag for ISA V2.06 Floating Point Conversion
target-ppc: Add ISA2.06 Float to Integer Instructions
target-ppc: Add ISA 2.06 fcfid[u][s] Instructions
softfloat: Fix exception flag handling for float32_to_float16()
softfloat: Factor out RoundAndPackFloat16 and
NormalizeFloat16Subnormal
softfloat: Refactor code handling various rounding modes
softfloat: Add support for ties-away rounding
target-ppc: Fix and enable fri[mnpz]
target-ppc: Add Flag for Power ISA V2.06 Floating Point Test
Instructions
target-ppc: Add ISA 2.06 ftdiv Instruction
target-ppc: Add ISA 2.06 ftsqrt
target-ppc: Enable frsqrtes on Power7 and Power8
target-ppc: Add ISA2.06 lfiwzx Instruction
fpu/softfloat.c | 657 ++++++++++++++++++++++++++++---------------
include/fpu/softfloat.h | 3 +-
include/qemu/host-utils.h | 28 ++
target-ppc/cpu.h | 15 +-
target-ppc/fpu_helper.c | 255 +++++++++--------
target-ppc/helper.h | 15 +
target-ppc/int_helper.c | 133 +++++++++
target-ppc/translate.c | 243 +++++++++++-----
target-ppc/translate_init.c | 23 ++-
util/host-utils.c | 75 +++++
10 files changed, 1025 insertions(+), 422 deletions(-)
