On 06.01.2014 07:52, Wenchao Xia wrote:
>> @@ -781,10 +784,10 @@ static void vnc_dpy_copy(DisplayChangeListener *dcl,
>> if ((s = w - w_lim) == 0)
>> break;
>> } else if (!x) {
>> -s = (16 - (dst_x % 16));
>> +s =
On 6 January 2014 07:56, Peter Crosthwaite wrote:
> On Mon, Jan 6, 2014 at 5:41 PM, Peter Maydell
> wrote:
>> That raises some more general design questions:
>> * how is this expected to interact with rom blob loading, -machine
>> firmware=,
>>etc?
>
> I guess it's not. The behavior of "-m
On Mon, Dec 30, 2013 at 01:29:08PM +0800, Hu Tao wrote:
> When cluster size is big enough it can lead offset overflow
> in qcow2_alloc_clusters_at(). This patch fixes it.
ping. and be more descriptive:
The allocation each time is stopped at L2 table boundary(see handle_alloc()),
so the possible m
> Le 6 janvier 2014 à 02:57, André Hentschel a écrit :
>
>
> From: André Hentschel
> Cc: Riku Voipio
> Signed-off-by: André Hentschel
[...]
> diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
> index cf08db5..b36f99c 100644
> --- a/linux-user/syscall_defs.h
> +++ b/linux-user/
ping~~
On Sat, Dec 21, 2013 at 9:47 AM, Jia Liu wrote:
> Hi Anthony,
>
> This is my OpenRISC patch queue for 1.8, it have been well tested, please
> pull.
>
> Thanks to Richard Henderson, he made the LD/ST updated.
> Thanks to Stefan Weil, he fixed a typo.
>
>
> Regards,
> Jia
>
>
> The followin
On 6 January 2014 08:45, Laurent Vivier wrote:
>
>> Le 6 janvier 2014 à 02:57, André Hentschel a écrit :
>> diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
>> index cf08db5..b36f99c 100644
>> --- a/linux-user/syscall_defs.h
>> +++ b/linux-user/syscall_defs.h
>> @@ -27,6 +27,9 @
Sorry, I propably just was lucky. It doesn't work without hugepages
also. The only thing I can do to make the 7870XT operate correclty under
guest is to make it show
qemu-system-x86_64: vfio_dma_map(0x7f01db7deec0, 0xc, 0xaff4,
0x2aaac00c) = -16 (Device or resource busy)
errors on sta
On 2014年01月05日 20:02, Amos Kong wrote:
This patch introduces a new monitor command to query QMP schema
information, the return data is a range of schema structs, which
contains the useful metadata to help management to check supported
features, QMP commands detail, etc.
It parses all json defini
On 12/27/2013 12:44 PM, Alexey Kardashevskiy wrote:
> On 12/27/2013 02:12 AM, Michael S. Tsirkin wrote:
>> On Fri, Dec 27, 2013 at 01:59:19AM +1100, Alexey Kardashevskiy wrote:
>>> On 12/27/2013 12:48 AM, Michael S. Tsirkin wrote:
On Thu, Dec 26, 2013 at 11:51:04PM +1100, Alexey Kardashevskiy
于 2014/1/6 2:02, Peter Lieven 写道:
> vnc_update_client currently scans the dirty bitmap of each client
> bitwise which is a very costly operation if only few bits are dirty.
> vnc_refresh_server_surface does almost the same.
> this patch optimizes both by utilizing the heavily optimized
> function f
On 2014年01月06日 14:48, Peter Lieven wrote:
On 06.01.2014 06:31, Fam Zheng wrote:
On 2014年01月06日 01:21, Peter Lieven wrote:
Signed-off-by: Peter Lieven
---
tests/qemu-iotests/013 |9 -
tests/qemu-iotests/013.out |2 +-
2 files changed, 5 insertions(+), 6 deletions(-)
dif
This is the command line:
qemu-system-armw -M versatilepb -kernel ..\BaseQemu\zImage -hda
..\BaseQemu\rootfs.squashfs -hdb ..\BaseQemu\flash.ext3 -append "root=/dev/sda
r" -net tap,ifname=TAP,script=no -net nic
I talked with the developer here and it seems that the bad speed is mainly due
to
On 2014年01月05日 20:02, Amos Kong wrote:
QMP schema is defined in a json file, it will be parsed by
qapi scripts and generate C files.
We want to return the schema information to management,
this patch converts the json file to a string table in a
C head file, then we can use the json content in Q
On 2 January 2014 01:57, Peter Crosthwaite wrote:
>
> When using QEMU in some terminal environments, char back-ends for serial
> devices can return EAGAIN for non trivial periods. This coupled with use
> of qemu_chr_fe_write_all() is a leading cause of:
>
> main-loop: WARNING: I/O thread spun for
> Le 6 janvier 2014 à 10:14, Peter Maydell a écrit :
>
>
> On 6 January 2014 08:45, Laurent Vivier wrote:
> >
> >> Le 6 janvier 2014 à 02:57, André Hentschel a écrit :
> >> diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
> >> index cf08db5..b36f99c 100644
> >> --- a/linux-use
On 21 December 2013 06:09, Christoffer Dall wrote:
> Implement support to save/restore the ARM KVM VGIC state from the
> kernel. The basic appraoch is to transfer state from the in-kernel VGIC
> to the emulated arm-gic state representation and let the standard QEMU
> vmstate save/restore handle s
On Fri, 03 Jan 2014 09:08:21 +1100
Alexey Kardashevskiy wrote:
>
> Please read the rest of this thread. It does not visibly break things but
> with this patch QEMU starts calling unassigned_mem_accepts() (normally
> silent) which is not a good sign.
>
>
>
Hmm... this is only because this patc
Implement an initial minimal set of EL0-visible system registers:
* NZCV
* FPCR
* FPSR
* CTR_EL0
* DCZID_EL0
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
Reviewed-by: Peter Crosthwaite
---
target-arm/cpu.h | 3 ++-
target-arm/helper.c| 61
From: Claudio Fontana
this patch adds support for C3.5.4 - C3.5.5
Conditional compare (both immediate and register)
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 73 +-
1
From: Peter Crosthwaite
Don't conditionalise GEM instantiation on networking attachments. The
device should always be present even if not attached to a network.
This allows for probing of the device by expectant guests (such as
OS's). This is needed because sysbus (or AXI in Xilinx's real hw ca
From: Christoffer Dall
TRIGGER can really mean mean anything (e.g. was it triggered, is it
level-triggered, is it edge-triggered, etc.). Rename to EDGE_TRIGGER to
make the code comprehensible without looking up the data structure.
Reviewed-by: Peter Maydell
Signed-off-by: Christoffer Dall
Mes
From: Peter Crosthwaite
If the UART back-end blocks, buffer in the Tx FIFO to try again later.
This stops the IO-thread busy waiting on char back-ends (which causes
all sorts of performance problems).
Signed-off-by: Peter Crosthwaite
Message-id:
4bea048b3ab38425701d82ccc1ab92545c26b79c.1388626
From: Christoffer Dall
To make the code slightly cleaner to look at and make the save/restore
code easier to understand, introduce this function to set the priority of
interrupts.
Reviewed-by: Peter Maydell
Signed-off-by: Christoffer Dall
Message-id: 1387606179-22709-3-git-send-email-christoff
From: Peter Crosthwaite
There is an inline duplication of the raw_read and raw_write function
bodies. Fix by just calling raw_read/raw_write instead.
Signed-off-by: Peter Crosthwaite
Reviewed-by: Peter Maydell
Message-id:
e69281b7e1462b346cb313cf0b89eedc0568125f.1388649290.git.peter.crosthwa.
From: "Michael S. Tsirkin"
commit 5ce4f35781028ce1aee3341e6002f925fdc7aaf3
"target-arm: A64: add set_pc cpu method"
introduces an array aarch64_cpus which is zero
size if this code is built without CONFIG_USER_ONLY.
In particular an attempt to iterate over this array produces a warning
under
From: Peter Crosthwaite
uart_rx_reset() called immediately above already does this. Remove.
Signed-off-by: Peter Crosthwaite
Message-id:
05e30826496cf2579084ed801ac0b2c0d0a3071f.1388626249.git.peter.crosthwa...@xilinx.com
Signed-off-by: Peter Maydell
---
hw/char/cadence_uart.c | 2 --
1 file
From: Alexander Graf
This patch adds emulation for the fmov instruction working on scalars
with an immediate payload.
Signed-off-by: Alexander Graf
[WN: Commit message tweak, rebase and use new infrastructure.]
Signed-off-by: Will Newton
Signed-off-by: Peter Maydell
Reviewed-by: Richard Hende
From: Peter Crosthwaite
Populate the TxFIFO with the Tx data before sending. Prepares
support for proper Tx flow control implementation.
Signed-off-by: Peter Crosthwaite
Message-id:
bdf7f8af2ef02839bea18665701bc2612f7baa6f.1388626249.git.peter.crosthwa...@xilinx.com
Signed-off-by: Peter Maydel
From: Alexander Graf
This patch adds emulation for the "Floating-point data-processing (3 source)"
group of instructions.
Signed-off-by: Alexander Graf
[WN: Commit message tweak, merged single and double precision patches.
Implement using muladd as suggested by Richard Henderson.]
Signed-off-b
From: Peter Crosthwaite
Rename this field to match the many other uses of "rx". Xilinx
docmentation (UG585) also refers to this as "RxFIFO".
Signed-off-by: Peter Crosthwaite
Message-id:
7386d7cee0ea175f7e53ed5ff045265528d34e32.1388626249.git.peter.crosthwa...@xilinx.com
Signed-off-by: Peter Ma
From: Alex Bennée
This adds support for the pre/post-index ld/st forms with immediate
offsets as well as the un-scaled immediate form (which are all
variations on the same 9-bit immediate instruction form).
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
From: Alexander Graf
When dumping the current CPU state, we can also get a request
to dump the FPU state along with the CPU's integer state.
Add support to dump the VFP state when that flag is set, so that
we can properly debug code that modifies floating point registers.
Signed-off-by: Alexand
Add a top level decoder skeleton for FP instructions.
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 170 -
1 file changed, 169 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/targe
From: Sergey Fedorov
Use c13_context field instead of c13_fcse for CONTEXTIDR register
definition.
Signed-off-by: Sergey Fedorov
Reviewed-by: Peter Crosthwaite
Reviewed-by: Peter Maydell
Message-id: 1387521191-15350-1-git-send-email-s.fedo...@samsung.com
Signed-off-by: Peter Maydell
---
tar
From: Peter Crosthwaite
As per current QOM conventions.
Signed-off-by: Peter Crosthwaite
Message-id:
a1e31bd62e9709ffb9b3efc6c120f83f30b7a660.1388626249.git.peter.crosthwa...@xilinx.com
Signed-off-by: Peter Maydell
---
hw/char/cadence_uart.c | 2 ++
1 file changed, 2 insertions(+)
diff --gi
From: Peter Crosthwaite
This tx timer implementation is flawed. Despite the controller
attempting to time the guest visable assertion of the TX-empty status
bit (and corresponding interrupt) the controller is still transmitting
characters instantaneously. There is also no sense of multiple charac
From: Alexander Graf
When setting rounding modes we currently just hardcode the numeric values
for rounding modes in a big switch statement.
With AArch64 support coming, we will need to refer to these rounding modes
at different places throughout the code though, so let's better give them
names
From: Claudio Fontana
The AArch64 linux-user support was written before but merged after
commit 4ce6243dc621 which cleaned up the handling of the clone()
syscall argument order, so we failed to notice that AArch64 also needs
TARGET_CLONE_BACKWARDS to be defined. Add this define so that clone
and
From: Claudio Fontana
This adds decoding support for C3.6.24 FP conditional select.
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 45 -
1 file changed, 44 insertions(+),
From: Alexander Graf
Add decoding for the exception generating instructions, and implement
SVC (syscalls) and BRK (software breakpoint).
Signed-off-by: Alexander Graf
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 51 +
The AArch64 equivalent of the traditional AArch32
cp15 coprocessor registers is the set of instructions
MRS/MSR/SYS/SYSL, which cover between them both true
system registers and the "operations with side effects"
such as cache maintenance which in AArch32 are mixed
in with other cp15 registers. Imp
Add a config for aarch64-linux-user, thereby enabling it as
a valid target.
Signed-off-by: Peter Maydell
Signed-off-by: Alexander Graf
Reviewed-by: Richard Henderson
---
default-configs/aarch64-linux-user.mak | 3 +++
1 file changed, 3 insertions(+)
create mode 100644 default-configs/aarch64-
From: Claudio Fontana
This adds decoding support for C3.6.23 FP Conditional Compare.
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 35 ++-
1 file changed, 34 insertions(+), 1 deletio
From: Alex Bennée
This adds support for the load/store forms using a register offset.
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 144 -
1 file changed, 143 insertions(+),
From: Alex Bennée
This patch adds emulation for the mov wide instructions
(MOVN, MOVZ, MOVK).
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 51 --
1 file changed, 49 insertio
In preparation for adding support for A64 load/store exclusive instructions,
widen the fields in the CPU state struct that deal with address and data values
for exclusives from 32 to 64 bits. Although in practice AArch64 and AArch32
exclusive accesses will be generally separate there are some odd t
The A64 128 bit vector registers are stored as a pair of
uint64_t values in the register array. This means that if
we're directly loading or storing a value of size less than
64 bits we must adjust the offset appropriately to account
for whether the host is bigendian or not. Provide utility
functio
From: Claudio Fontana
Add decoding support for C3.6.22 Floating-point compare.
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/helper-a64.c| 45
target-arm/helper-a64.h| 4 +++
target-arm/tran
On Sun, Dec 29, 2013 at 02:32:50PM +0200, Marcel Apfelbaum wrote:
> It seems that iasl has an issue when disassembles
> some ACPI tables using the command line:
> iasl -e DSDT -e SSDT -d HPET
> I opened a bug on iasl project:
> https://github.com/acpica/acpica/issues/20
>
> Modified the iasl comma
From: Alexander Graf
Adds support for Load Register (literal), both normal
and SIMD/FP forms.
Signed-off-by: Alexander Graf
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 47
Il 06/01/2014 06:36, Li Guang ha scritto:
>> dma_memory_write() work?
>
> what about cpu_physical_memory_write_rom ?
Sorry, I missed that load_image_targphys is already doing the right
thing on reset.
Paolo
Il 06/01/2014 08:56, Peter Crosthwaite ha scritto:
> > What are the guidelines for when to use one or the other?
>
> "-machine firmware=" if you want to load a firmware blob in a board
> specific way. This if you want to place a blob in memory at an
> arbitrary location on reset.
"-machine firmwa
On 06.01.2014 11:09, Fam Zheng wrote:
On 2014年01月06日 14:48, Peter Lieven wrote:
On 06.01.2014 06:31, Fam Zheng wrote:
On 2014年01月06日 01:21, Peter Lieven wrote:
Signed-off-by: Peter Lieven
---
tests/qemu-iotests/013 |9 -
tests/qemu-iotests/013.out |2 +-
2 files change
The framebuffer is needlessly mapped (PROT_READ | PROT_WRITE), map it
PROT_READ instead.
The framebuffer is unmapped by replacing the framebuffer pages with
anonymous shared memory, calling mmap. Check for return errors and print
a warning.
Signed-off-by: Stefano Stabellini
CC: Gerd Hoffmann
CC
Update the generic cpreg support code to also handle AArch64:
AArch64-visible registers coexist in the same hash table with
AArch32-visible ones, with a bit in the hash key distinguishing
them.
Signed-off-by: Peter Maydell
Reviewed-by: Peter Crosthwaite
---
target-arm/cpu.h| 78 +++
From: Michael Matz
This implement exclusive loads/stores for aarch64 along the lines of
arm32 and ppc implementations. The exclusive load remembers the address
and loaded value. The exclusive store throws an an exception which uses
those values to check for equality in a proper exclusive region.
From: Alex Bennée
Implement the non-carry forms of addition and subtraction
(immediate, extended register and shifted register).
This includes the code to calculate NZCV if the instruction
calls for setting the flags.
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
Reviewed-by: Richard
On 2014年01月06日 20:21, Peter Lieven wrote:
On 06.01.2014 11:09, Fam Zheng wrote:
On 2014年01月06日 14:48, Peter Lieven wrote:
On 06.01.2014 06:31, Fam Zheng wrote:
On 2014年01月06日 01:21, Peter Lieven wrote:
Signed-off-by: Peter Lieven
---
tests/qemu-iotests/013 |9 -
tests/qemu
From: Alexander Graf
This patch adds emulation for the "Floating-point data-processing (2 source)"
group of instructions.
Signed-off-by: Alexander Graf
[WN: Commit message tweak, merge single and double precision patches. Rebase
and update to new infrastructure. Incorporate FMIN/FMAX support p
Commit bcf2b7d introduced new 256k seabios files. However,
they were not installed.
Signed-off-by: Peter Lieven
---
Makefile |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index bdff4e4..807054b 100644
--- a/Makefile
+++ b/Makefile
@@ -290,7 +290,7 @@
On 2 January 2014 22:21, Tom Musta wrote:
> The comment preceding the float64_to_uint64 routine suggests that
> the implementation is broken. And this is, indeed, the case.
>
> This patch properly implements the conversion of a 64-bit floating
> point number to an unsigned, 64 bit integer.
>
> Th
On 2 January 2014 22:21, Tom Musta wrote:
> This patch adds the float32_to_uint64() routine, which converts a
> 32-bit floating point number to an unsigned 64 bit number.
>
> This contribution can be licensed under either the softfloat-2a or -2b
> license.
>
> Signed-off-by: Tom Musta >
Reviewed-
From: Peter Crosthwaite
Don't reset the uart as an init step. Register the reset function as a
proper reset fn instead.
Signed-off-by: Peter Crosthwaite
Message-id:
d82cd2e65e5a6f8b6deeecb6cced61f0bf3f8c89.1388626249.git.peter.crosthwa...@xilinx.com
Signed-off-by: Peter Maydell
---
hw/char/c
Hi all
This idea is to modify QEMU's Makefiles, plus implementing some stubs to
make it possible to tailor QEMU to a smaller binary.
The current setup for Xen on X86 is to build i386-softmmu, and uses this
single binary for two purposes:
1. serves as device emulator for HVM guest.
2. serves as PV
From: Peter Crosthwaite
The can_receive logic was only taking into account the RxFIFO
occupancy. RxFIFO population is only used for the echo and normal modes
however. Improve the logic to correctly return the true number of
receivable characters based on the current mode:
Normal mode: RxFIFO vac
From: Claudio Fontana
This patch adds support for C3.5.3 Add/subtract (with carry):
instructions ADC, ADCS, SBC, SBCS.
Signed-off-by: Claudio Fontana
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 105 -
On Mon, Jan 6, 2014 at 10:13 PM, Paolo Bonzini wrote:
> Il 06/01/2014 08:56, Peter Crosthwaite ha scritto:
>> > What are the guidelines for when to use one or the other?
>>
>> "-machine firmware=" if you want to load a firmware blob in a board
>> specific way. This if you want to place a blob in m
The cpregs APIs used by the decoder (get_arm_cp_reginfo() and
cp_access_ok()) currently take either a CPUARMState* or an ARMCPU*.
This is problematic for the A64 decoder, which doesn't pass the
environment pointer around everywhere the way the 32 bit decoder
does. Adjust the parameters these functi
From: Peter Crosthwaite
This should be rechecked on bus write accesses as such accesses may
change the underlying state that generates the interrupt. Particular
relevant for when the guest touches the interrupt status or mask.
Signed-off-by: Peter Crosthwaite
Message-id:
1c250cd61b7b8de492fbc8
From: Alex Bennée
Now the AArch64 targets are in mainline we can include them in our
Travis test matrix.
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
---
.travis.yml | 1 +
1 file changed, 1 insertion(+)
diff --git a/.travis.yml b/.travis.yml
index 90f1676..c7ff4da 100644
--- a/.t
Refactor the code in various functions which calculates rounding
increments given the current rounding mode, so that instead of a
set of nested if statements we have a simple switch statement.
This will give us a clean place to add the case for the new
tiesAway rounding mode.
Signed-off-by: Peter
We implement a number of float-to-integer conversions using conversion
to an integer type with a wider range and then a check against the
narrower range we are actually converting to. If we find the result to
be out of range we correctly raise the Invalid exception, but we must
also suppress other
On 6 January 2014 12:54, Peter Lieven wrote:
> Commit bcf2b7d introduced new 256k seabios files. However,
> they were not installed.
This is a dup of this patch by Eduardo from last month:
http://patchwork.ozlabs.org/patch/299233/
thanks
-- PMM
Ping -- who's going to take this patch? Maybe it should
go via -trivial?
thanks
-- PMM
On 9 December 2013 23:33, Eduardo Habkost wrote:
> The default machine-type (pc-i440fx-2.0) now requires bios-256k.bin, but
> "make install" isn't installing it, so qemu-system-x86_64 won't run out
> of the bo
On 06.01.2014 14:12, Peter Maydell wrote:
On 6 January 2014 12:54, Peter Lieven wrote:
Commit bcf2b7d introduced new 256k seabios files. However,
they were not installed.
This is a dup of this patch by Eduardo from last month:
http://patchwork.ozlabs.org/patch/299233/
Thanks for the pointer.
On 01/05/2014 09:39 PM, Stefan Hajnoczi wrote:
> Commit 9117b47717ad208b12786ce88eacb013f9b3dd1c ("qcow2: Change default
> for new images to compat=1.1") changed the default qcow2 image format
> version but forgot to update qemu-doc.texi and qemu-img.texi.
>
> Signed-off-by: Stefan Hajnoczi
> ---
On 6 January 2014 13:17, Peter Lieven wrote:
> On 06.01.2014 14:12, Peter Maydell wrote:
>
> On 6 January 2014 12:54, Peter Lieven wrote:
>
> Commit bcf2b7d introduced new 256k seabios files. However,
> they were not installed.
>
> This is a dup of this patch by Eduardo from last month:
> http://
On 06.01.2014 14:17, Peter Maydell wrote:
On 6 January 2014 13:17, Peter Lieven wrote:
On 06.01.2014 14:12, Peter Maydell wrote:
On 6 January 2014 12:54, Peter Lieven wrote:
Commit bcf2b7d introduced new 256k seabios files. However,
they were not installed.
This is a dup of this patch by Ed
On Mon, 2014-01-06 at 13:43 +0200, Michael S. Tsirkin wrote:
> On Sun, Dec 29, 2013 at 02:32:50PM +0200, Marcel Apfelbaum wrote:
> > It seems that iasl has an issue when disassembles
> > some ACPI tables using the command line:
> > iasl -e DSDT -e SSDT -d HPET
> > I opened a bug on iasl project:
>
On Mon, Jan 6, 2014 at 10:54 PM, Wei Liu wrote:
> Hi all
>
> This idea is to modify QEMU's Makefiles, plus implementing some stubs to
> make it possible to tailor QEMU to a smaller binary.
>
> The current setup for Xen on X86 is to build i386-softmmu, and uses this
> single binary for two purposes
On Mon, 2014-01-06 at 12:54 +, Wei Liu wrote:
> Hi all
>
> This idea is to modify QEMU's Makefiles, plus implementing some stubs to
> make it possible to tailor QEMU to a smaller binary.
>
> The current setup for Xen on X86 is to build i386-softmmu, and uses this
> single binary for two purpo
From: Alexander Graf
This patch adds emulation for the "Data-processing (3 source)"
family of instructions, namely MADD, MSUB, SMADDL, SMSUBL, SMULH,
UMADDL, UMSUBL, UMULH.
Signed-off-by: Alexander Graf
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
--
From: Will Newton
Add support for the AArch64 floating-point <-> integer conversion
instructions to disas_fpintconv. In the process we can rearrange
and simplify the detection of unallocated encodings a little.
We also correct a typo in the instruction encoding diagram for this
instruction group:
This patch adds support for those instructions in the "Floating-point
data-processing (1 source)" group which are simple 32-bit-to-32-bit
or 64-bit-to-64-bit operations (ie everything except FCVT between
single/double/half precision).
We put the new round-to-int helpers in helper.c because they w
From: Will Newton
Use the helpers provided for getting the correct FPSR and FPCR
values for the signal context.
Signed-off-by: Will Newton
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
linux-user/signal.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
dif
From: Alexander Graf
This patch adds emulation for the instruction group labeled
"Floating-point <-> fixed-point conversions" in the ARM ARM.
Namely this includes the instructions SCVTF, UCVTF, FCVTZS, FCVTZU
(scalar, fixed-point).
Signed-off-by: Alexander Graf
[WN: Commit message tweak, rebas
Add the float to 16 bit integer conversion routines. These can be
trivially implemented in terms of the int32_to_float* routines, but
providing them makes our API more symmetrical and can simplify callers.
Signed-off-by: Peter Maydell
---
include/fpu/softfloat.h | 21 +
1 fil
From: Alex Bennée
This adds support for the forms of ld/st with a 12 bit
unsigned immediate offset.
Signed-off-by: Alex Bennée
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/translate-a64.c | 89 +-
1 file changed, 88 in
From: Will Newton
Define the full set of floating point to fixed point conversion
helpers required to support AArch64.
Signed-off-by: Will Newton
Signed-off-by: Peter Maydell
Reviewed-by: Richard Henderson
---
target-arm/helper.c | 11 ++-
target-arm/helper.h | 16
2
From: Tom Musta
This patch adds the float32_to_uint64() routine, which converts a
32-bit floating point number to an unsigned 64 bit number.
This contribution can be licensed under either the softfloat-2a or -2b
license.
Signed-off-by: Tom Musta
Reviewed-by: Peter Maydell
Signed-off-by: Peter
changes since commit f976b09ea2493fd41c98aaf6512908db0bae:
PPC: Fix compilation with TCG debug (2013-12-22 19:15:55 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20140106
for you to fetch changes up to
The common pattern for system registers in a 64-bit capable ARM
CPU is that when in AArch32 the cp15 register is a view of the
bottom 32 bits of the 64-bit AArch64 system register; writes in
AArch32 leave the top half unchanged. The most natural way to
model this is to have the state field in the C
From: Tom Musta
The float64_to_uint32 has several flaws:
- for numbers between 2**32 and 2**64, the inexact exception flag
may get incorrectly set. In this case, only the invalid flag
should be set.
test pattern: 425F81378DC0CD1F / 0x1.f81378dc0cd1fp+38
- for numbers between 2*
From: Tom Musta
The comment preceding the float64_to_uint64 routine suggests that
the implementation is broken. And this is, indeed, the case.
This patch properly implements the conversion of a 64-bit floating
point number to an unsigned, 64 bit integer.
This contribution can be licensed under
In preparation for adding conversions between float16 and float64,
factor out code currently done inline in the float16<=>float32
conversion functions into functions RoundAndPackFloat16 and
NormalizeFloat16Subnormal along the lines of the existing versions
for the other float types.
Note that we c
From: Tom Musta
The float64_to_uint32_round_to_zero routine is incorrect.
For example, the following test pattern:
425F81378DC0CD1F / 0x1.f81378dc0cd1fp+38
will erroneously set the inexact flag.
This patch re-implements the routine to use the float64_to_uint64_round_to_zero
routine. If s
From: Will Newton
The VFP conversion helpers for A32 round to zero as this is the only
rounding mode supported. Rename these helpers to make it clear that
they round to zero and are not suitable for use in the AArch64 code.
Signed-off-by: Will Newton
Signed-off-by: Peter Maydell
Reviewed-by: R
Add support for FCVT between half, single and double precision.
Signed-off-by: Peter Maydell
---
target-arm/helper.c| 20 +
target-arm/helper.h| 2 ++
target-arm/translate-a64.c | 75 +-
3 files changed, 96 insertions(+), 1
This patchset completes the FP emulation, leaving us with only
Neon (and CRC32) to go to complete the user-mode emulation.
Most of this is fixing issues and adding new features to softfloat.
(As usual, all Linaro authored softfloat patches are licensed under
either softfloat-2a or softfloat-2b, at
Add the conversion functions float16_to_float64() and
float64_to_float16(), which will be needed for the ARM
A64 instruction set.
Signed-off-by: Peter Maydell
---
fpu/softfloat.c | 75 +
include/fpu/softfloat.h | 2 ++
2 files changed, 77
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