On 23/12/13 03:02, Peter Bartoli wrote:
Hi Peter,
Very welcome! Thanks for the awesome software. It's allowed me to put my
SparcServer 5 out to pasture as a demonstration machine. Really, really hoping
that it supports the tcx with OBP at some point soon ... that'd be very cool.
I filed a
Hi Folks:
I'm writing this letter mainly for help and suggestion.
I'm using qemu-aarch64[1] from matz's repository, which actually is
not official.
with matz's repo, and trying to build a small gentoo rootfs, I
encountered a problem with gcc-4.9.0 and if only commit[2] is
included, I have rep
On Fri, Dec 20, 2013 at 07:03:57PM +0100, Paolo Bonzini wrote:
> Il 20/12/2013 12:57, Amos Kong ha scritto:
> > { 'type': 'DataObjectBase',
> > 'data': { '*name': 'str', 'type': 'str' } }
> > { 'union': 'DataObjectMemberType',
> > 'discriminator': {},
> > 'data': { 'reference': 'str',
> >
On Mon, Dec 23, 2013 at 4:09 PM, Dennis Lan (dlan)
wrote:
> Hi Folks:
>I'm writing this letter mainly for help and suggestion.
>I'm using qemu-aarch64[1] from matz's repository, which actually is
> not official.
> with matz's repo, and trying to build a small gentoo rootfs, I
> encountered
On 23 December 2013 03:45, Lauren E Guckert wrote:
> IN TRANSLATE.C:
> DISAS_INSN FUNCTION:
>
> ++TCGv t0 = tcg_temp_new();
> ++TCGv t1 = tcg_temp_new();
> ++t0= pc_start; t1 = b;
> ++tcg_gen_helper_fast_trace(t0,t1);
The TCGv type represents a TCG value. You have to
use the TCG f
On 23 December 2013 07:43, Fedorov Sergey wrote:
>
> On 12/20/2013 06:33 PM, Peter Maydell wrote:
>> This sounds like it could work, though there are some wrinkles for
>> registers with readfns/writefns -- do we have extra s vs ns read/write
>> functions, or just one set of functions which has to
Implement x86_cpu_unrealizefn() for corresponding x86_cpu_realizefn(),
which is mostly used to clean the apic related allocation and vmstates
at here.
Signed-off-by: Chen Fan
---
hw/i386/kvm/apic.c | 8
hw/intc/apic.c | 10 ++
hw/intc/apic_common.c
This motion is preparing for refactoring vCPU apic subsequently.
Signed-off-by: Chen Fan
---
cpu-exec.c| 2 +-
cpus.c| 5 ++---
hw/i386/kvmvapic.c| 8 +++-
hw/i386/pc.c | 17 -
target-i386/cpu-qom.h | 4
ta
Rename variable 'cpu_added_notifier' to 'cpu_hotplug_notifier' for
adding remove vcpu notifier support.
Signed-off-by: Chen Fan
---
hw/acpi/piix4.c | 10 +-
hw/i386/pc.c| 2 +-
include/sysemu/sysemu.h | 2 +-
qom/cpu.c | 10 +-
4 files changed,
Via implementing ACPI standard methods _EJ0 in ACPI table, after Guest OS remove
one vCPU online, the fireware will store removed bitmap to QEMU, then QEMU could
know to notify the assigned vCPU of exiting. meanwhile, intruduce the QOM
command
'cpu-del' to remove vCPU from QEMU itself. currently,
add cpu hot-remove interface pc_hot_del_cpu() for unrealizing vcpu device.
when using 'cpu-del' command, not need to specify vcpuid, the last one cpu
will be removed.
Signed-off-by: Chen Fan
---
hw/i386/pc.c | 19 +++
hw/i386/pc_piix.c| 3 ++-
include/hw/boards.h |
Move struct HotplugEventType from file piix4.c to file qom/cpu.c,
and add struct CPUNotifier for supporting UNPLUG cpu notifier.
Signed-off-by: Chen Fan
---
hw/acpi/piix4.c | 8 ++--
include/qom/cpu.h | 10 ++
qom/cpu.c | 6 +-
3 files changed, 17 insertions(+), 7 del
After ACPI get a signal to eject a vCPU, then it will notify
the vCPU thread to exit in KVM, and the vCPU must be removed from CPU list，
before the vCPU really removed, there will release the all related vCPU objects.
Signed-off-by: Chen Fan
---
cpus.c | 39
When OS ejected a vcpu (like: echo 1 > /sys/bus/acpi/devices/LNXCPUXX/eject),
it would call acpi EJ0 method, the firmware need to write the new cpumap, QEMU
would know which vcpu need to be ejected.
TODO: for now QEMU only supported that cpu was deleted sequentially from the
last
one in OS, in th
add interface cpu_common_unrealizefn() for emiting vcpu unplug
notifier to ACPI, then ACPI could send sci interrupt
to OS for hot-remove vcpu.
Signed-off-by: Chen Fan
---
qom/cpu.c | 12
1 file changed, 12 insertions(+)
diff --git a/qom/cpu.c b/qom/cpu.c
index 728b83b..78038ab 1006
Hi all. I need to write some qemu block driver (like sheepdog or ceph).
Where i can find some docs/tips/tutorials what functions i need to implement?
Thank you.
--
Vasiliy Tolstov,
e-mail: v.tols...@selfip.ru
jabber: v...@selfip.ru
This test will run only if iasl is installed on the host machine.
The test plan:
1. Dumps the ACPI tables as AML on the disk.
2. Runs iasl to disassembly the tables into ASL files.
3. Runs iasl to disassembly the offline AML files into ASL files.
4. Compares the ASL files.
The test runs for bo
Added unit-test's expected aml files to be compared
with the actual ACPI tables.
Signed-off-by: Marcel Apfelbaum
---
tests/acpi-test-data/pc/APIC | Bin 0 -> 120 bytes
tests/acpi-test-data/pc/DSDT | Bin 0 -> 4407 bytes
tests/acpi-test-data/pc/FACP | Bin 0 -> 116 bytes
tests/acpi-test-data/p
Ensure configure will set-up links for the files
if the build is created in other directory.
Signed-off-by: Marcel Apfelbaum
---
configure | 4
1 file changed, 4 insertions(+)
diff --git a/configure b/configure
index edfea95..c30be12 100755
--- a/configure
+++ b/configure
@@ -4744,6 +4744,
The test:
- runs only if iasl is installed on the host machine.
- the test plan:
1. Dumps the ACPI tables as AML on the disk.
2. Runs iasl to disassembly the tables into ASL files.
3. Runs iasl to disassembly the offline AML files.
3. Compares them with expected offline ASL files.
-
On 23.12.2013, at 07:48, Hervé Poussineau wrote:
> Hi,
>
> Andreas Färber a écrit :
>> Hi,
>> Am 05.11.2013 00:09, schrieb Hervé Poussineau:
>>> Raven datasheet explains where firmware lives in system memory, so do
>>> it there instead of in board code. Other boards using the same PCI
>>> host
On Sun, Dec 22, 2013 at 03:51:28PM +0100, Igor Mammedov wrote:
> On Mon, 16 Dec 2013 21:53:07 +0200
> "Michael S. Tsirkin" wrote:
>
> > On Fri, Dec 13, 2013 at 05:22:14PM +0100, Igor Mammedov wrote:
> > > .. and report range used by it to OSPM via _CRS.
> > > PRST is needed in SSDT since its base
commit 5ce4f35781028ce1aee3341e6002f925fdc7aaf3
"target-arm: A64: add set_pc cpu method"
introduces an array aarch64_cpus which is zero
size if this code is built without CONFIG_USER_ONLY.
In particular an attempt to iterate over this array produces a warning:
CCaarch64-softmmu/target-ar
On Mon, Dec 23, 2013 at 12:13:23PM +0200, Marcel Apfelbaum wrote:
> The test:
> - runs only if iasl is installed on the host machine.
> - the test plan:
>1. Dumps the ACPI tables as AML on the disk.
>2. Runs iasl to disassembly the tables into ASL files.
>3. Runs iasl to disassembly t
On Mon, Dec 23, 2013 at 12:13:26PM +0200, Marcel Apfelbaum wrote:
> This test will run only if iasl is installed on the host machine.
> The test plan:
> 1. Dumps the ACPI tables as AML on the disk.
> 2. Runs iasl to disassembly the tables into ASL files.
> 3. Runs iasl to disassembly the offline
12.12.2013 01:00, Stefan Weil wrote:
> hw_error is already used for target-arm and target-s390x.
> Using it for target-m68k fixes this compiler warning with Darwin because
> hw_error is declared with QEMU_NORETURN:
Thanks, applied to the trivial-patches queue.
/mjt
19.12.2013 01:09, Stefan Weil wrote:
> In the new form most lines of the code now look like the final output:
> there is no leading echo command and the lines are shorter.
>
> The resulting output is nearly identical: the only difference is a blank
> character which was deliberately removed:
> Th
19.12.2013 01:30, Stefan Weil wrote:
> The help message uses $python and displays its value, so that macro
> should be tested and set early.
Thanks, applied to the trivial-patches queue.
/mjt
20.12.2013 17:44, Ingo van Lil wrote:
> It is possible to pre-define a character device with the -chardev option
> and reference its id as serial device. The man page does not mention this
> feature.
Thanks, applied to the trivial-patches queue.
/mjt
22.12.2013 18:32, Stefan Weil wrote:
> The row and column values use only a very limited range (-1 ... 7),
> so a byte value is sufficient.
Thanks, applied to the trivial-patches queue.
/mjt
22.12.2013 18:22, Stefan Weil wrote:
> The mapping is a hardware feature, so it is relatively constant.
Thanks, applied to the trivial-patches queue.
/mjt
22.12.2013 23:42, Stefan Weil wrote:
> cgcc reported a duplicate initialisation. Mainstone includes a matrix
> keyboard where two different positions map to 'space'.
Thanks, applied to the trivial-patches queue.
/mjt
On Mon, 2013-12-23 at 14:02 +0200, Michael S. Tsirkin wrote:
> On Mon, Dec 23, 2013 at 12:13:23PM +0200, Marcel Apfelbaum wrote:
> > The test:
> > - runs only if iasl is installed on the host machine.
> > - the test plan:
> >1. Dumps the ACPI tables as AML on the disk.
> >2. Runs iasl to
Aneesh Kumar K.V wrote:
> "Kirill A. Shutemov" writes:
>
> > Kirill A. Shutemov wrote:
> >> Currently we have few issues with P9_STATS_GEN:
> >>
> >> - We don't try to read st_gen anything except files or directories, but
> >>still set P9_STATS_GEN bit in st_result_mask. It may mislead clie
On Mon, 2013-12-23 at 14:06 +0200, Michael S. Tsirkin wrote:
> On Mon, Dec 23, 2013 at 12:13:26PM +0200, Marcel Apfelbaum wrote:
> > This test will run only if iasl is installed on the host machine.
> > The test plan:
> > 1. Dumps the ACPI tables as AML on the disk.
> > 2. Runs iasl to disassembl
Hi Peter,
On 21/12/13 18:59, Peter Maydell wrote:
>> @@ -4526,6 +4529,7 @@ case "$target_name" in
>>\( "$target_name" = "ppc64" -a "$cpu" = "ppc" \) -o \
>>\( "$target_name" = "ppc"-a "$cpu" = "ppc64" \) -o \
>>\( "$target_name" = "ppcemb" -a "$cpu" = "ppc64" \) -o \
>
On 23 December 2013 11:56, Michael S. Tsirkin wrote:
> commit 5ce4f35781028ce1aee3341e6002f925fdc7aaf3
> "target-arm: A64: add set_pc cpu method"
>
> introduces an array aarch64_cpus which is zero
> size if this code is built without CONFIG_USER_ONLY.
> In particular an attempt to iterate over
Il 23/12/2013 13:37, Peter Maydell ha scritto:
> At a minimum, if we take this approach we should add TODO comments
> to the effect that the NULL terminator and the if() can be removed
> when the first real AArch64 CPU is added.
>
> I think I'd rather put the if (!info->name) continue into the fun
On 23 December 2013 12:50, Paolo Bonzini wrote:
> Il 23/12/2013 13:37, Peter Maydell ha scritto:
>> At a minimum, if we take this approach we should add TODO comments
>> to the effect that the NULL terminator and the if() can be removed
>> when the first real AArch64 CPU is added.
>>
>> I think I'
On Mon, 23 Dec 2013 13:26:37 +0200
"Michael S. Tsirkin" wrote:
> On Sun, Dec 22, 2013 at 03:51:28PM +0100, Igor Mammedov wrote:
> > On Mon, 16 Dec 2013 21:53:07 +0200
> > "Michael S. Tsirkin" wrote:
> >
> > > On Fri, Dec 13, 2013 at 05:22:14PM +0100, Igor Mammedov wrote:
> > > > .. and report r
Thanks for digging into this.
I am indeed getting the same ramblock error. So it's good that there appears to
be a fix for it.
Also if I understand it correctly this particular issue only affects the 1.6.0
snapshots so given that most of my snapshots are still on 1.3.x a direct
upgrade to 1.7+ w
Yes, my understanding of the bug is that 1.7+ should load your 1.3.x
images and then snapshots taken on 1.7.x should be OK into the future.
I don't think there's currently a way of fixing those 1.6.0 snapshots;
that workaround will let you load them in 1.7, but I think if you were
then to take a s
Am 23.12.2013 13:59, schrieb Peter Maydell:
> On 23 December 2013 12:50, Paolo Bonzini wrote:
>> Il 23/12/2013 13:37, Peter Maydell ha scritto:
>>> At a minimum, if we take this approach we should add TODO comments
>>> to the effect that the NULL terminator and the if() can be removed
>>> when the
On 23 December 2013 13:32, Stefan Weil wrote:
> Am 23.12.2013 13:59, schrieb Peter Maydell:
>> On 23 December 2013 12:50, Paolo Bonzini wrote:
>>> Il 23/12/2013 13:37, Peter Maydell ha scritto:
At a minimum, if we take this approach we should add TODO comments
to the effect that the NUL
Am 23.12.2013 13:37, schrieb Peter Maydell:
> On 23 December 2013 11:56, Michael S. Tsirkin wrote:
>> commit 5ce4f35781028ce1aee3341e6002f925fdc7aaf3
>> "target-arm: A64: add set_pc cpu method"
>>
>> introduces an array aarch64_cpus which is zero
>> size if this code is built without CONFIG_US
On Dec 20, 2013, at 11:55 AM, Alexander Graf wrote:
>
> On 19.12.2013, at 17:04, Aneesh Kumar K.V
> wrote:
>
>> From: "Aneesh Kumar K.V"
>>
>> Targets like ppc64 support different typed of KVM, one which use
>> hypervisor mode and the other which doesn't. Add a new machine
>> property kvm-
On 23 December 2013 13:45, Andreas Färber wrote:
> While I share your sentiment wrt this workaround, what's the status of
> getting a real 64-bit CPU applied? Isn't the Cortex-A57/A53 CPU
> independent of whether we have all MPCore etc. pieces in place? That
> would seem the most elegant solution
On Mon, Dec 23, 2013 at 01:41:50PM +, Peter Maydell wrote:
> On 23 December 2013 13:32, Stefan Weil wrote:
> > Am 23.12.2013 13:59, schrieb Peter Maydell:
> >> On 23 December 2013 12:50, Paolo Bonzini wrote:
> >>> Il 23/12/2013 13:37, Peter Maydell ha scritto:
> At a minimum, if we take
On Mon, Dec 23, 2013 at 12:37:41PM +, Peter Maydell wrote:
> On 23 December 2013 11:56, Michael S. Tsirkin wrote:
> > commit 5ce4f35781028ce1aee3341e6002f925fdc7aaf3
> > "target-arm: A64: add set_pc cpu method"
> >
> > introduces an array aarch64_cpus which is zero
> > size if this code is
On 23 December 2013 14:15, Michael S. Tsirkin wrote:
> OK, ack my patch then? I'll add a comment
> /* TODO: remove when we support more CPUs. */
Post an updated patch (with TODO comments in both
places) and I'll ack it.
thanks
-- PMM
commit 5ce4f35781028ce1aee3341e6002f925fdc7aaf3
"target-arm: A64: add set_pc cpu method"
introduces an array aarch64_cpus which is zero
size if this code is built without CONFIG_USER_ONLY.
In particular an attempt to iterate over this array produces a warning
under gcc 4.8.2:
CCaarch64-s
On 23 December 2013 14:24, Michael S. Tsirkin wrote:
> Changes from v1:
> added a TODO so we remember why the extra line is here.
>
> target-arm/cpu64.c | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c
> index 04ce879..a9d6939 100644
> ---
Am 22.12.2013 19:04, schrieb Aurelien Jarno:
> On Sat, Dec 07, 2013 at 10:44:51AM +1300, Richard Henderson wrote:
>> The size of tlb_table is 4k on a 64-bit host. For overwriting
>> memory at this size, cacheline tricks can help.
>>
>> Signed-off-by: Richard Henderson
>> ---
>> cputlb.c | 19 ++-
On Mon, Dec 23, 2013 at 02:06:27PM +0100, Igor Mammedov wrote:
> On Mon, 23 Dec 2013 13:26:37 +0200
> "Michael S. Tsirkin" wrote:
>
> > On Sun, Dec 22, 2013 at 03:51:28PM +0100, Igor Mammedov wrote:
> > > On Mon, 16 Dec 2013 21:53:07 +0200
> > > "Michael S. Tsirkin" wrote:
> > >
> > > > On Fri,
commit 5ce4f35781028ce1aee3341e6002f925fdc7aaf3
"target-arm: A64: add set_pc cpu method"
introduces an array aarch64_cpus which is zero
size if this code is built without CONFIG_USER_ONLY.
In particular an attempt to iterate over this array produces a warning
under gcc 4.8.2:
CCaarch64-s
Am 23.12.2013 15:52, schrieb Michael S. Tsirkin:
> commit 5ce4f35781028ce1aee3341e6002f925fdc7aaf3
> "target-arm: A64: add set_pc cpu method"
>
> introduces an array aarch64_cpus which is zero
> size if this code is built without CONFIG_USER_ONLY.
> In particular an attempt to iterate over this
On Mon, Dec 23, 2013 at 02:18:47PM +0200, Marcel Apfelbaum wrote:
> On Mon, 2013-12-23 at 14:02 +0200, Michael S. Tsirkin wrote:
> > On Mon, Dec 23, 2013 at 12:13:23PM +0200, Marcel Apfelbaum wrote:
> > > The test:
> > > - runs only if iasl is installed on the host machine.
> > > - the test plan:
On 23 December 2013 14:52, Michael S. Tsirkin wrote:
> commit 5ce4f35781028ce1aee3341e6002f925fdc7aaf3
> "target-arm: A64: add set_pc cpu method"
>
> introduces an array aarch64_cpus which is zero
> size if this code is built without CONFIG_USER_ONLY.
> In particular an attempt to iterate over
On Mon, Dec 23, 2013 at 02:22:38PM +0200, Marcel Apfelbaum wrote:
> On Mon, 2013-12-23 at 14:06 +0200, Michael S. Tsirkin wrote:
> > On Mon, Dec 23, 2013 at 12:13:26PM +0200, Marcel Apfelbaum wrote:
> > > This test will run only if iasl is installed on the host machine.
> > > The test plan:
> > >
Am 23.12.2013 10:04, schrieb Chen Fan:
> This motion is preparing for refactoring vCPU apic subsequently.
>
> Signed-off-by: Chen Fan
> ---
> cpu-exec.c| 2 +-
> cpus.c| 5 ++---
> hw/i386/kvmvapic.c| 8 +++-
> hw/i386/pc.c | 17 +++
From: "Aneesh Kumar K.V"
Targets like ppc64 support different typed of KVM, one which use
hypervisor mode and the other which doesn't. Add a new machine
property kvm-type that helps in selecting the respective ones
We also add a new QEMUMachine callback get_vm_type that helps
in mapping the strin
Alexander Graf writes:
> On Dec 20, 2013, at 11:55 AM, Alexander Graf wrote:
>
>>
>> On 19.12.2013, at 17:04, Aneesh Kumar K.V
>> wrote:
>>
>>> From: "Aneesh Kumar K.V"
>>>
>>> Targets like ppc64 support different typed of KVM, one which use
>>> hypervisor mode and the other which doesn't.
The following changes since commit f976b09ea2493fd41c98aaf6512908db0bae:
PPC: Fix compilation with TCG debug (2013-12-22 19:15:55 +0100)
are available in the git repository at:
git://git.kernel.org/pub/scm/virt/kvm/mst/qemu.git tags/for_anthony
for you to fetch changes up to 5bf58abf1cb
From: Laszlo Ersek
Check whether the firmware is not hidden by other memory regions.
Qemu is started in paused mode: it shouldn't try to interpret generated
garbage.
Signed-off-by: Laszlo Ersek
Signed-off-by: Michael S. Tsirkin
---
tests/i440fx-test.c | 81 +++
Document the logic behind the below/above 4G split.
Signed-off-by: Michael S. Tsirkin
---
hw/i386/pc_piix.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index acb9445..832e20c 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -61,
From: Igor Mammedov
... and rename it into acpi_update_sci() since it changes
SCI on only on PM registers status.
Signed-off-by: Igor Mammedov
Signed-off-by: Michael S. Tsirkin
---
include/hw/acpi/acpi.h | 8
hw/acpi/core.c | 18 ++
hw/acpi/ich9.c | 2
From: Paolo Bonzini
Post-order is the only sensible direction for the reset signals.
For example, suppose pre-order is used and the parent has some data
structures that cache children state (for example a list of active
requests). When the reset method is invoked on the parent, these caches
coul
From: Gerd Hoffmann
Map 3G (i440fx) of memory below 4G, so the RAM pieces
are nicely aligned to gigabyte borders.
Keep old memory layout for (a) old machine types and (b) in case all
memory fits below 4G and thus we don't have to split RAM into pieces
in the first place. The later makes sure th
From: Laszlo Ersek
This patch allows the user to usefully specify
-drive file=img_1,if=pflash,format=raw,readonly \
-drive file=img_2,if=pflash,format=raw
on the command line. The flash images will be mapped under 4G in their
reverse unit order -- that is, with their base addresses progress
From: Paolo Bonzini
qbus_reset_all can be used instead. There is no semantic change
because pcibus_reset returns 1 and takes care of the device
tree traversal.
Signed-off-by: Paolo Bonzini
Signed-off-by: Michael S. Tsirkin
---
include/hw/pci/pci.h | 1 -
hw/pci/pci.c | 8 ++--
hw
From: Gerd Hoffmann
Make the 32bit pci hole start at end of ram, so all possible address
space is covered.
We used to try and make addresses aligned so they are easier to cover
with MTRRs, but since they are cosmetic on KVM, this is probably not
worth worrying about.
Of course the firmware can u
From: Laszlo Ersek
Similarly to commit 1d9358e6
("libqtest: New qtest_end() to go with qtest_start()").
Signed-off-by: Laszlo Ersek
Signed-off-by: Michael S. Tsirkin
---
tests/i440fx-test.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/tests/i440fx-test.c b/te
From: Laszlo Ersek
The current two GTest cases, /i440fx/defaults and /i440fx/pam can share a
qemu process, but the next two cases will need dedicated instances. It is
messy (and order-dependent) to dynamically configure GTest cases one by
one to start, stop, or keep the current qtest (*); let's j
From: Paolo Bonzini
pci_device_reset will deassert the INTX pins, and this will make the
irq_count array all-zeroes. Check that this is the case, and remove
the existing loop which might even unsync irq_count and irq_state.
Signed-off-by: Paolo Bonzini
Signed-off-by: Michael S. Tsirkin
---
h
From: Igor Mammedov
Hardcoded GPE0 mask isn't really needed. Since GPE0_STS initialized
with all bits cleared and only QEMU itself can set bits there (i.e.
guest can only clear bits in it). So guest can't triger SCI
by setting _STS & _EN bits and there is not reason to mask out not
supported _STS
commit 5ce4f35781028ce1aee3341e6002f925fdc7aaf3
"target-arm: A64: add set_pc cpu method"
introduces an array aarch64_cpus which is zero
size if this code is built without CONFIG_USER_ONLY.
In particular an attempt to iterate over this array produces a warning
under gcc 4.8.2:
CCaarch64-s
From: Paolo Bonzini
Resetting should be done in post-order, not pre-order. However,
qdev_walk_children and qbus_walk_children do not allow this. Fix
it by adding two extra arguments to the functions.
Signed-off-by: Paolo Bonzini
Signed-off-by: Michael S. Tsirkin
---
include/hw/qdev-core.h |
From: Igor Mammedov
Fix bogus CPU hotplug GPE handler.
Make Q35 CPU hotplug GPE handler match PIIX4 one, since
CPU hotplug event is triggered by GPE0.2 register.
Signed-off-by: Igor Mammedov
Signed-off-by: Michael S. Tsirkin
---
hw/i386/q35-acpi-dsdt.dsl | 4 ++--
1 file changed, 2 insertions
From: Paolo Bonzini
This got lost in a rebase.
Reported-by: Stefan Hajnoczi
Signed-off-by: Paolo Bonzini
Signed-off-by: Michael S. Tsirkin
---
hw/virtio/virtio.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c
index 144b9ca..a001e66 100644
--- a/
From: Laszlo Ersek
The blob is 64K in size and contains 0x00..0xFF repeatedly.
The client code added to main() wouldn't make much sense in the long term.
It helps with debugging and it silences gcc about create_blob_file() being
unused, and we'll replace it in the next patch anyway.
Signed-off-
From: Igor Mammedov
it fixes IRQ storm since guest isn't able to lower SCI IRQ
after it has been handled when it clears GPE event.
Signed-off-by: Igor Mammedov
Signed-off-by: Michael S. Tsirkin
---
hw/acpi/ich9.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/acpi/ich9.c b/hw/acpi/ich
On Mon, Dec 23, 2013 at 02:01:13AM +1100, Alexey Kardashevskiy wrote:
> On 12/23/2013 01:46 AM, Alexey Kardashevskiy wrote:
> > On 12/22/2013 09:56 PM, Michael S. Tsirkin wrote:
> >> On Sun, Dec 22, 2013 at 02:01:23AM +1100, Alexey Kardashevskiy wrote:
> >>> Hi!
> >>>
> >>> I am having a problem wi
On Mon, 23 Dec 2013 16:48:49 +0200
"Michael S. Tsirkin" wrote:
> On Mon, Dec 23, 2013 at 02:06:27PM +0100, Igor Mammedov wrote:
> > On Mon, 23 Dec 2013 13:26:37 +0200
> > "Michael S. Tsirkin" wrote:
> >
> > > On Sun, Dec 22, 2013 at 03:51:28PM +0100, Igor Mammedov wrote:
> > > > On Mon, 16 Dec
On Fri, Dec 20, 2013 at 03:10:37PM +0100, Mian M. Hamayun wrote:
> From: Antonios Motakis
>
> Add structures for passing vhost-user messages over a unix domain socket.
> This is the equivalent to the existing vhost-kernel ioctls.
>
> Connect to the named unix domain socket. The system call sendm
On Mon, Dec 23, 2013 at 05:24:30PM +0100, Igor Mammedov wrote:
> On Mon, 23 Dec 2013 16:48:49 +0200
> "Michael S. Tsirkin" wrote:
>
> > On Mon, Dec 23, 2013 at 02:06:27PM +0100, Igor Mammedov wrote:
> > > On Mon, 23 Dec 2013 13:26:37 +0200
> > > "Michael S. Tsirkin" wrote:
> > >
> > > > On Sun,
On 12/23/13 17:24, Igor Mammedov wrote:
> On Mon, 23 Dec 2013 16:48:49 +0200
> "Michael S. Tsirkin" wrote:
>
>> On Mon, Dec 23, 2013 at 02:06:27PM +0100, Igor Mammedov wrote:
>>> On Mon, 23 Dec 2013 13:26:37 +0200
>>> "Michael S. Tsirkin" wrote:
Interesting. This seems to imply that it can
On 8 December 2013 22:59, Peter Maydell wrote:
> This patchset is a collection of minor Cocoa UI patches:
> * the 'pass command key through when mousegrabbed' patch I sent
>earlier (included here for convenience since the others in
>the series would otherwise trivially conflict)
> * typo
On 23.12.2013, at 16:40, Aneesh Kumar K.V
wrote:
> From: "Aneesh Kumar K.V"
>
> Targets like ppc64 support different typed of KVM, one which use
> hypervisor mode and the other which doesn't. Add a new machine
> property kvm-type that helps in selecting the respective ones
> We also add a new
From: Igor Mammedov
Signed-off-by: Igor Mammedov
Signed-off-by: Michael S. Tsirkin
---
hw/i386/acpi-dsdt-cpu-hotplug.dsl | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/i386/acpi-dsdt-cpu-hotplug.dsl
b/hw/i386/acpi-dsdt-cpu-hotplug.dsl
index c96ac42..995b415 100644
--- a/hw/i386/acpi-ds
From: "Aneesh Kumar K.V"
Correctly update the htab_mask using the return value of
KVM_PPC_ALLOCATE_HTAB ioctl. Also we don't update sdr1
on GET_SREGS for HV. So don't update htab_mask if sdr1
is found to be zero. Fix the pte index calculation to be
same as that found in the kernel
Signed-off-by:
From: "Aneesh Kumar K.V"
We will use this in later patches to make sure we use the right load
functions when copying hpte entries.
Signed-off-by: Aneesh Kumar K.V
---
hw/ppc/spapr.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index e99a66170661..3
From: "Aneesh Kumar K.V"
With kvm enabled, we store the hash page table information in the hypervisor.
Use ioctl to read the htab contents. Without this we get the below error when
trying to read the guest address
(gdb) x/10 do_fork
0xc0098660 : Cannot access memory at address
0xc00
The 1.7.4 version of SeaBIOS has now been released. For more
information on the release, please see:
http://seabios.org/Releases
New in this release:
* Support for obtaining ACPI tables directly from QEMU.
* Initial support for XHCI USB controllers (initially for QEMU only).
* Support for boot
Am 23.12.2013 16:40, schrieb Aneesh Kumar K.V:
> From: "Aneesh Kumar K.V"
>
> Targets like ppc64 support different typed of KVM, one which use
"types" - Alex, please fix. :)
> hypervisor mode and the other which doesn't. Add a new machine
> property kvm-type that helps in selecting the respecti
Am 20.12.2013 02:00, schrieb Alexander Graf:
> Tom Musta (19):
> Declare and Enable VSX
> Add MSR VSX and Associated Exception
> Add VSX Instruction Decoders
> Add VSR to Global Registers
> Add lxvd2x
> Add stxvd2x
> Add xxpermdi
> Add lxsdx
> A
On 23.12.2013, at 19:08, Andreas Färber wrote:
> Am 20.12.2013 02:00, schrieb Alexander Graf:
>> Tom Musta (19):
>> Declare and Enable VSX
>> Add MSR VSX and Associated Exception
>> Add VSX Instruction Decoders
>> Add VSR to Global Registers
>> Add lxvd2x
>> Add stx
Alexander Graf a écrit :
On 23.12.2013, at 07:48, Hervé Poussineau wrote:
Hi,
Andreas Färber a écrit :
Hi,
Am 05.11.2013 00:09, schrieb Hervé Poussineau:
Raven datasheet explains where firmware lives in system memory, so do
it there instead of in board code. Other boards using the same PCI
On 23 December 2013 06:48, Hervé Poussineau wrote:
> So, this patch is a small functional change, as it adds a copy of the
> firmware in a new range 0xfff0-0xfff7, but I think we can live with
> it.
>
> We'll be able to remove it once we switch to another firmware which uses the
> right re
Public bug reported:
Note this is using the not-yet-upstream aarch64 patches from:
https://github.com/susematz/qemu/tree/aarch64-1.6
This binary:
http://oirase.annexia.org/tmp/test.gz
runs OK on real aarch64 hardware. It is a statically linked Linux
binary which (if successful) wil
Peter Maydell a écrit :
On 23 December 2013 06:48, Hervé Poussineau wrote:
So, this patch is a small functional change, as it adds a copy of the
firmware in a new range 0xfff0-0xfff7, but I think we can live with
it.
We'll be able to remove it once we switch to another firmware which u
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