We use the rom infrastructure to write firmware and/or initial kernel
blobs into guest address space. So we're basically emulating the cache
off phase on very early system bootup.
That phase is usually responsible for clearing the instruction cache for
anything it writes into cachable memory, to e
From: Tom Musta
This patch adds the VSX scalar move instructions:
- xsabsdp (Scalar Absolute Value Double-Precision)
- xsnabspd (Scalar Negative Absolute Value Double-Precision)
- xsnegdp (Scalar Negate Double-Precision)
- xscpsgndp (Scalar Copy Sign Double-Precision)
A common generator
From: Tom Musta
This patch adds the stxvd2x instruction.
Signed-off-by: Tom Musta
Signed-off-by: Anton Blanchard
Signed-off-by: Alexander Graf
---
target-ppc/translate.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
in
From: Tom Musta
This patch adds VSX VSRs to the the list of global register indices.
More specifically, it adds the lower halves of the first 32 VSRs to
the list of global register indices. The upper halves of the first
32 VSRs are already defined via cpu_fpr[]. And the second 32 VSRs
are alrea
From: Tom Musta
This patch adds the VSX Splat Word (xxsplatw) instruction.
This is the first instruction to use the UIM immediate field
and consequently a decoder is also added.
V2: reworked implementation per Richard Henderson's comments.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henders
When we have 2 separate qdev devices that both create a qbus of the
same type without specifying a bus name or device name, we end up
with two buses of the same name, such as ide.0 on the Mac machines:
dev: macio-ide, id ""
bus: ide.0
type IDE
dev: macio-ide, id ""
bus: ide.0
On 2013年12月19日 21:12, Stefan Hajnoczi wrote:
On Tue, Dec 17, 2013 at 08:00:00PM +0800, Fam Zheng wrote:
@@ -1511,48 +1521,55 @@ static int vmdk_create_extent(const char *filename,
int64_t filesize,
header.check_bytes[3] = 0xa;
/* write all the data */
-ret = qemu_write_full(fd,
This improves vmdk_create to use bdrv_* functions to replace qemu_open
and other fd functions. The error handling are improved as well. One
difference is that bdrv_pwrite will round up buffer to sectors, so for
description file, an extra bdrv_truncate is used in the end to drop
inding zeros.
Notes
From: Tom Musta
This patch adds the Load VSX Vector Word*4 Indexed (lxvw4x)
instruction.
V2: changed to use deposit_i64 per Richard Henderson's review.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Signed-off-by: Alexander Graf
---
target-ppc/translate.
From: Tom Musta
This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx)
instruction.
The lower 8 bytes of the target register are undefined; this
implementation leaves those bytes unaltered.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Signed-off-
From: Tom Musta
This patch adds the Load VSX Vector Doubleword & Splat Indexed
(lxvdsx) instruction.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Signed-off-by: Alexander Graf
---
target-ppc/translate.c | 16
1 file changed, 16 insertio
From: Alexey Kardashevskiy
This adds very basic handlers for ibm,get-system-parameter and
ibm,set-system-parameter RTAS calls.
The only parameter handled at the moment is
"platform-processor-diagnostics-run-mode" which is always disabled and
does not support changing. This is expected to make
"p
From: Tom Musta
This patch adds support for the VSX bit of the PowerPC Machine
State Register (MSR) as well as the corresponding VSX Unavailable
exception.
The VSX bit is added to the defined bits masks of the Power7 and
Power8 CPU models.
Signed-off-by: Tom Musta
Signed-off-by: Anton Blanchar
Since last use of PPC_DUMP_CPU by whoever he/she was, env->tlb became
a union and POWERPC CPU class got QOM'ed so defining PPC_DUMP_CPU
breaks compile.
This fixes compiler errors.
Signed-off-by: Alexey Kardashevskiy
---
target-ppc/translate_init.c | 5 +++--
1 file changed, 3 insertions(+), 2 d
On Thu, Dec 19, 2013 at 3:00 AM, Luiz Capitulino wrote:
> From: Paolo Bonzini
>
> Add two commands that are the monitor counterparts of -object. The commands
> have the same Visitor-based implementation, but use different kinds of
> visitors so that the HMP command has a DWIM string-based syntax
From: Alexey Kardashevskiy
IBM POWERPC processors encode PVR as a CPU family in higher 16 bits and
a CPU version in lower 16 bits. Since there is no significant change
in behavior between versions, there is no point to add every single CPU
version in QEMU's CPU list. Also, new CPU versions of alr
From: Alexey Kardashevskiy
So far POWER7+ was a part of POWER7 family. However it has a different
PVR base value so in order to support PVR masks, it needs a separate
family class.
This adds a new family class, PVR base and mask values and moves
Power7+ v2.1 CPU to a new family. The class init f
From: Tom Musta
This patch adds the VSX Merge High Word and VSX Merge Low Word
instructions.
V2: Now implemented using deposit (per Richard Henderson's comment)
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Signed-off-by: Alexander Graf
---
target-ppc/translate.c | 41
On 20.12.2013, at 03:14, Alexey Kardashevskiy wrote:
> Since last use of PPC_DUMP_CPU by whoever he/she was, env->tlb became
> a union and POWERPC CPU class got QOM'ed so defining PPC_DUMP_CPU
> breaks compile.
>
> This fixes compiler errors.
>
> Signed-off-by: Alexey Kardashevskiy
Thanks, a
On Thu, Dec 19, 2013 at 3:00 AM, Luiz Capitulino wrote:
> From: Paolo Bonzini
>
> Signed-off-by: Paolo Bonzini
> Reviewed-By: Igor Mammedov
> Signed-off-by: Luiz Capitulino
> ---
> qom/object.c | 9 +++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/qom/object.c b/qo
From: Tom Musta
This patch adds the VSX Shift Left Double by Word Immediate
(xxsldwi) instruction.
Signed-off-by: Tom Musta
Signed-off-by: Alexander Graf
---
target-ppc/translate.c | 62 ++
1 file changed, 62 insertions(+)
diff --git a/target-p
From: Tom Musta
This patch adds the vector move instructions:
- xvabsdp - Vector Absolute Value Double-Precision
- xvnabsdp - Vector Negative Absolute Value Double-Precision
- xvnegdp - Vector Negate Double-Precision
- xvcpsgndp - Vector Copy Sign Double-Precision
- xvabssp - Vector Ab
From: Paolo Bonzini
spapr-nvram's drive property is currently connected to a non-existent
"-machine nvram=" option. Instead, tie it to -pflash like
other non-volatile RAM devices. This provides the following possibilities
for adding a backend for the sPAPR non-volatile RAM:
* -pflash filename
From: Alexey Kardashevskiy
The SPAPR specification says that the RMA starts at the LPAR's logical
address 0 and is the first logical memory block reported in
the LPAR’s device tree.
So SLOF only maps the first block and that block needs to span
the full RMA.
This makes sure that the RMA area is
From: Tom Musta
This patch adds the Store VSX Scalar Doubleword Indexed (stxsdx)
instruction.
Signed-off-by: Tom Musta
Reviewed-by: Richard Henderson
Reviewed-by: Paolo Bonzini
Signed-off-by: Alexander Graf
---
target-ppc/translate.c | 15 +++
1 file changed, 15 insertions(+)
d
There's no good reason to call our bus "pci" rather than let the default
bus name take over ("pci.0").
The big downside to calling it different from anyone else is that tools
that pass -device get confused. They are looking for a bus "pci.0" rather
than "pci".
To make life easier for everyone, le
From: Tom Musta
This patch adds the flag POWERPC_FLAG_VSX to the list of defined
flags and also adds this flag to the list of supported features of
the Power7 and Power8 CPUs. Additionally, the VSX instructions
are added to the list of TCG-enabled instruction.
Signed-off-by: Tom Musta
Signed-o
On 12/05/2013 08:39 PM, Alexey Kardashevskiy wrote:
> On 11/21/2013 03:08 PM, Alexey Kardashevskiy wrote:
>> Here are few reworks for spapr-pci PHB which I'd like to have to support
>> VFIO.
>> QOM, errors printing, traces, nothing really serious. Thanks!
>>
>> Alexey Kardashevskiy (4):
>> spapr
On 12/05/2013 08:39 PM, Alexey Kardashevskiy wrote:
> On 11/20/2013 04:39 PM, Alexey Kardashevskiy wrote:
>> This adds a put_tce() callback to the SPAPR TCE TABLE device class.
>> The new callback allows to have different IOMMU types such as upcoming
>> VFIO IOMMU and it will be used more by the up
On Wed, Dec 18, 2013 at 07:15:43PM +, Stefano Stabellini wrote:
> Hi all,
> the xenpv machine provides Xen paravirtualized backends for console,
> disk and framebuffer. xenfb in particular is the only open source
> framebuffer backend available.
> On ARM we don't need QEMU to emulate any hardwa
On Fri, Dec 20, 2013 at 10:49 AM, Anthony Liguori wrote:
> On Wed, Dec 18, 2013 at 8:59 AM, Luiz Capitulino
> wrote:
>> The following changes since commit e157b8fdd412d48eacfbb8c67d3d58780154faa3:
>>
>> Merge remote-tracking branch 'bonzini/virtio' into staging (2013-12-13
>> 11:10:33 -0800)
> -Original Message-
> From: Michael S. Tsirkin [mailto:m...@redhat.com]
> Sent: Friday, December 20, 2013 12:02 AM
> To: Alexander Graf
> Cc: Bhushan Bharat-R65777; Wood Scott-B07421; QEMU Developers; qemu-ppc
> Subject: Re: [PATCH 2/2] ppc-e500: implement PCI INTx routing
>
> On Thu, D
On Thu, Dec 19, 2013 at 7:11 PM, Peter Maydell wrote:
> On 19 December 2013 06:01, Peter Crosthwaite
> wrote:
>> On Wed, Dec 18, 2013 at 1:12 AM, Peter Maydell
>> wrote:
>>> +*key = ENCODE_AA64_CP_REG(r2->cp, r->crn, crm,
>>> + r-
On Wed, Dec 18, 2013 at 1:12 AM, Peter Maydell wrote:
> Update the generic cpreg support code to also handle AArch64:
> AArch64-visible registers coexist in the same hash table with
> AArch32-visible ones, with a bit in the hash key distinguishing
> them.
>
> Signed-off-by: Peter Maydell
> ---
>
On Fri, Dec 20, 2013 at 04:15:09AM +, bharat.bhus...@freescale.com wrote:
>
>
> > -Original Message-
> > From: Michael S. Tsirkin [mailto:m...@redhat.com]
> > Sent: Friday, December 20, 2013 12:02 AM
> > To: Alexander Graf
> > Cc: Bhushan Bharat-R65777; Wood Scott-B07421; QEMU Develop
On Thu, Nov 28, 2013 at 12:05:33PM +0530, Bharat Bhushan wrote:
> This patch adds pci pin to irq_num routing callback
> Without this patch we gets below warning
>
> "
> PCI: Bug - unimplemented PCI INTx routing (e500-pcihost)
> qemu-system-ppc64: PCI: Bug - unimplemented PCI INTx routing (e500
It is bad that same key was specified twice, especially when a union have
two branches with same condition. This patch can prevent it.
Signed-off-by: Wenchao Xia
Reviewed-by: Eric Blake
---
scripts/qapi.py |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/scripts/qapi.py
Later other scripts will need to check the enum values.
Signed-off-by: Wenchao Xia
Reviewed-by: Eric Blake
---
scripts/qapi.py| 18 ++
tests/qapi-schema/comments.out |2 +-
tests/qapi-schema/qapi-schema-test.out |4 +++-
3 files changed,
This series address two issues:
1. support using enum as discriminator in union.
For example, if we have following define in qapi schema:
{ 'enum': 'EnumOne',
'data': [ 'value1', 'value2', 'value3' ] }
{ 'type': 'UserDefBase0',
'data': { 'base-string0': 'str', 'base-enum0': 'EnumOne' } }
Bef
By default, any union will automatically generate a enum type as
"[UnionName]Kind" in C code, and it is duplicated when the discriminator
is specified as a pre-defined enum type in schema. After this patch,
the pre-defined enum type will be really used as the switch case
condition in generated C co
Later both qapi-types.py and qapi-visit.py need a common function
for enum name generation.
Signed-off-by: Wenchao Xia
Reviewed-by: Eric Blake
---
scripts/qapi-types.py | 10 --
scripts/qapi.py | 10 ++
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/s
It will check whether the values specified are written correctly,
and whether all enum values are covered, when discriminator is a
pre-defined enum type
Signed-off-by: Wenchao Xia
Reviewed-by: Eric Blake
---
scripts/qapi-visit.py | 17 +
scripts/qapi.py | 31 ++
After this patch, hidden enum type BlockdevOptionsKind will not
be generated, and other API can use enum BlockdevDriver.
Signed-off-by: Wenchao Xia
Reviewed-by: Eric Blake
---
qapi-schema.json | 14 +-
1 files changed, 13 insertions(+), 1 deletions(-)
diff --git a/qapi-schema.jso
Test for inherit and complex union.
Signed-off-by: Wenchao Xia
---
tests/qapi-schema/qapi-schema-test.json | 22 ++
tests/qapi-schema/qapi-schema-test.out |9 +++
tests/test-qmp-input-visitor.c | 93 +
tests/test-qmp-output-visitor.c | 116 +
Signed-off-by: Wenchao Xia
---
docs/qapi-code-gen.txt |8 +++-
scripts/qapi-visit.py |6 ++
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/docs/qapi-code-gen.txt b/docs/qapi-code-gen.txt
index a2e7921..c92add9 100644
--- a/docs/qapi-code-gen.txt
+++ b/docs/qapi-co
Prior to this patch, qapi-visit.py used custom code to generate enum
names used for handling a qapi union. Fix it to instead reuse common
code, with identical generated results, and allowing future updates to
generation to only need to touch one place.
Signed-off-by: Wenchao Xia
Reviewed-by: Eric
Alexander Graf writes:
> On 19.12.2013, at 07:55, Aneesh Kumar K.V
> wrote:
>
>> Alexander Graf writes:
>>
>>> On 07.11.2013, at 15:31, Aneesh Kumar K.V
>>> wrote:
>>>
From: "Aneesh Kumar K.V"
With kvm enabled, we store the hash page table information in the
hypervis
Now "enum AIOContext" will generate AIO_CONTEXT instead of A_I_O_CONTEXT,
"X86CPU" will generate X86_CPU instead of X86_C_P_U.
Signed-off-by: Wenchao Xia
Reviewed-by: Eric Blake
---
include/qapi/qmp/qerror.h |2 +-
scripts/qapi.py | 26 +++---
target-i386/cpu
Currently, if compile with Werror option, the error message shows
below:
GEN config-host.h
GEN trace/generated-tracers.h
CHK version_gen.h
GEN trace/generated-tracers.c
CCvl.o
vl.c: In function ‘get_boot_devices_list’:
vl.c:1257:21: error: ‘bootpath’ may be used uninitial
Use c13_context field instead of c13_fcse for CONTEXTIDR register
definition.
Signed-off-by: Sergey Fedorov
Reviewed-by: Peter Crosthwaite
---
target-arm/helper.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 6ebd7dc..d52d
PowerISA defines LPCR SPR number as 318=0x13E but QEMU uses the value of
316.
This fixes the definition of LPCR SPR.
Signed-off-by: Alexey Kardashevskiy
---
target-ppc/cpu.h| 2 +-
target-ppc/translate_init.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/tar
PowerISA 2.04+ puts MMUCFG and MMUCSR0 SPRs to "E" (embedded) category so
remove it from POWER7/8 class as it is "S" (server) category.
Signed-off-by: Alexey Kardashevskiy
---
target-ppc/translate_init.c | 46 -
1 file changed, 46 deletions(-)
diff --
SPR_750FX_HID2 and L2CR are not defined in 970* user manuals nor POWER5
bookIV nor PowerISA 2.04, the numbers assigned to them are not defined
either so remove them.
Signed-off-by: Alexey Kardashevskiy
---
target-ppc/translate_init.c | 39 ---
1 file changed,
The 970GX definition was added in 2007 and it made sense then but this
version has never been released to the markets and it does not exist in
the real world so there is no point in emulating it.
This removes 970GX.
Signed-off-by: Alexey Kardashevskiy
---
target-ppc/STATUS | 9
This removes not supported SPR from CPU classes.
Alexey Kardashevskiy (5):
target-ppc: fix LPCR SPR number
target-ppc: remove powerpc 970gx
target-ppc: fix SPR_CTRL/SPR_UCTRL register numbers
target-ppc: remove embedded MMU SPRs from 970, P5+/7/7+/8
target-ppc: remove unsupported SPRs fr
Assuming that "U" in SPR_UCTRL is for "user", there is inconsistency with
970 user manuals/P5-bookIV/PowerISA204 which define the number as:
priviledged
# spr5-9 spr0-4 name mtspr mfspr len cat
136 00100 01000 CTRL -no32 S
152 00100 11000 CTRL yes-3
Hi,
this patch or one of the two following patches breaks compilation with
--enable-debug (lots of TCGv_i32 - TCGv_i64 mismatches).
Cheers,
Stefan
Am 20.12.2013 02:00, schrieb Alexander Graf:
> From: Tom Musta
>
> This patch adds the VSX Select (xxsel) instruction.
>
> The xxsel instruction has
As other tests, the image file is created in /tmp other than current
dir. Thus there will not be an unignored file under tests for intree
build.
Signed-off-by: Fam Zheng
---
tests/acpi-test.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tests/acpi-test.c b/tests/acpi-test.
2013/12/18 Konrad Rzeszutek Wilk
> On Wed, Dec 18, 2013 at 07:15:43PM +, Stefano Stabellini wrote:
> > Hi all,
> > the xenpv machine provides Xen paravirtualized backends for console,
> > disk and framebuffer. xenfb in particular is the only open source
> > framebuffer backend available.
> >
Il 20/12/2013 08:05, Fam Zheng ha scritto:
> As other tests, the image file is created in /tmp other than current
> dir. Thus there will not be an unignored file under tests for intree
> build.
>
> Signed-off-by: Fam Zheng
> ---
> tests/acpi-test.c | 2 +-
> 1 file changed, 1 insertion(+), 1 del
will it be solved in the next qemu upload, right? how long will it take
to have it on launchpad builders?
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1042388
Title:
qemu: Unsupported syscall: 257
On Thu, 2013-11-28 at 15:41 +0100, Igor Mammedov wrote:
> On Wed, 9 Oct 2013 17:43:08 +0800
> Chen Fan wrote:
>
> > Via implementing ACPI standard methods _EJ0 in bios, after Guest OS hot
> > remove
> > one vCPU, it is able to send a signal to QEMU, then QEMU could notify
> > the assigned vCPU o
On Thu, Dec 19, 2013 at 12:25:57PM +0530, Aneesh Kumar K.V wrote:
> Alexander Graf writes:
>
> > This breaks if you run a 64-bit guest on a 32-bit host trying to
> > access memory beyond 4GB. In that case htab_base is hwaddr (64bit)
> > while uint8_t is only 32bit wide.
>
> Wow!! didn't know tha
On 19 December 2013 05:49, Christoffer Dall wrote:
> On Thu, Nov 28, 2013 at 05:43:54PM +, Peter Maydell wrote:
>> The other possibility is that it's a correct implementation
>> of 11MPCore GIC semantics -- the documentation of the
>> 11MPCore definitely says that level triggered interrupts
>>
On Wed, Dec 18, 2013 at 01:53:56PM +0200, Alexander Binun wrote:
> We are trying to monitor the traffic (network packets etc) between VMs in
> KVM. We succeeded to get the address of the system call table (see
> http://syprog.blogspot.co.il/2011/10/hijack-linux-system-calls-part-iii.html)
> and
On 19 December 2013 06:01, Peter Crosthwaite
wrote:
> On Wed, Dec 18, 2013 at 1:12 AM, Peter Maydell
> wrote:
>> +*key = ENCODE_AA64_CP_REG(r2->cp, r->crn, crm,
>> + r->opc0, opc1, opc2);
>
> You have mixed terminology here with "o
On Wed, Dec 18, 2013 at 06:05:39PM +0100, Markus Armbruster wrote:
> Andreas Färber writes:
>
> > I had a brief look at this series. Dropping redundant fields certainly
> > sounds good and after the lengthy QOM'ifications of IDE devices we seem
> > to no longer break any devices, but whether to c
On Wed, 2013-12-18 at 19:20 +0200, Michael S. Tsirkin wrote:
> On Wed, Dec 18, 2013 at 06:49:24PM +0200, Marcel Apfelbaum wrote:
> > On Wed, 2013-12-18 at 18:33 +0200, Michael S. Tsirkin wrote:
> > > On Wed, Dec 18, 2013 at 06:27:12PM +0200, Marcel Apfelbaum wrote:
> > > > On Wed, 2013-12-18 at 17:
On Thu, 2013-12-19 at 11:37 +0200, Marcel Apfelbaum wrote:
> On Wed, 2013-12-18 at 19:20 +0200, Michael S. Tsirkin wrote:
> > On Wed, Dec 18, 2013 at 06:49:24PM +0200, Marcel Apfelbaum wrote:
> > > On Wed, 2013-12-18 at 18:33 +0200, Michael S. Tsirkin wrote:
> > > > On Wed, Dec 18, 2013 at 06:27:12
On 12/17/2013 05:26 PM, Juan Quintela wrote:
Performance is important in this function, and we want to optimize even further.
Signed-off-by: Juan Quintela
---
kvm-all.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/kvm-all.c b/kvm-all.c
index 3937754..308dfba 100
On 12/17/2013 05:26 PM, Juan Quintela wrote:
Signed-off-by: Juan Quintela
---
kvm-all.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/kvm-all.c b/kvm-all.c
index 308dfba..cb62ba4 100644
--- a/kvm-all.c
+++ b/kvm-all.c
@@ -382,7 +382,8 @@ static int
kvm_get_dirty
On 17 December 2013 15:26, Juan Quintela wrote:
> @@ -399,8 +401,9 @@ static int
> kvm_get_dirty_pages_log_range(MemoryRegionSection *section,
> page_number = (i * HOST_LONG_BITS + j) * hpratio;
> addr1 = page_number * TARGET_PAGE_SIZE;
> addr =
On 12/17/2013 05:26 PM, Juan Quintela wrote:
We want to have all the functions that handle directly the dirty
bitmap near. We will change it later.
Signed-off-by: Juan Quintela
---
include/exec/ram_addr.h | 31 +++
kvm-all.c | 27 ++-
On 12/17/2013 05:26 PM, Juan Quintela wrote:
If bitmaps are aligned properly, use bitmap operations. If they are
not, just use old bit at a time code.
Signed-off-by: Juan Quintela
---
include/exec/ram_addr.h | 54 -
1 file changed, 36 insertio
On Thu, Dec 19, 2013 at 11:49:21AM +0200, Marcel Apfelbaum wrote:
> > > Basically something like the below (warning: completely untested,
> > > sorry).
> > I tested and it works fine for both windows and linux guests!
> Actually it doesn't work :(
> I was testing a "working hack", not the master br
On 12/17/2013 05:26 PM, Juan Quintela wrote:
This function is the only bit where we care about speed.
Signed-off-by: Juan Quintela
---
arch_init.c | 34 --
1 file changed, 20 insertions(+), 14 deletions(-)
diff --git a/arch_init.c b/arch_init.c
index 0e8c8b5.
On 12/17/2013 05:26 PM, Juan Quintela wrote:
We use the old code if the bitmaps are not aligned
Signed-off-by: Juan Quintela
---
arch_init.c | 38 +-
1 file changed, 29 insertions(+), 9 deletions(-)
diff --git a/arch_init.c b/arch_init.c
index 2cd3d00..77
On 12/18/2013 02:48 PM, Corey Bryant wrote:
This fixes a bug where we weren't exiting if seccomp_init() failed.
Signed-off-by: Corey Bryant
---
qemu-seccomp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/qemu-seccomp.c b/qemu-seccomp.c
index cf07869..b7c1253 100644
--- a/qemu-seccom
On 12/16/2013 08:23 AM, Andreas Färber wrote:
> Am 04.12.2013 06:51, schrieb Peter Crosthwaite:
>> On Wed, Dec 4, 2013 at 1:42 AM, Paolo Bonzini wrote:
>>> From: Hervé Poussineau
>>>
>>> We should not modify the type hash table while it is being iterated on.
>>> Assert that it does not happen.
>>
On 19 December 2013 07:27, Fedorov Sergey wrote:
> Yes, this banking scheme makes state changing events quite heavy. But
> maintaining the active copies allows to keep translation table walking code
> untouched. I think there is a trade-off between state changing and
> translation table walking ov
Hi,
> So that would look like a SeaBIOS feature freeze on Dec 6th and target
> release date of Dec 20th. Works for me.
/me got sick, so with the xmas/newyear holidays being just around the
corner that implies I'll be offline for the rest of the year.
Kevin will most likely tag v1.7.4 neverthe
On Thu, Dec 19, 2013 at 9:38 PM, Peter Maydell wrote:
> On 19 December 2013 07:27, Fedorov Sergey wrote:
>> Yes, this banking scheme makes state changing events quite heavy. But
>> maintaining the active copies allows to keep translation table walking code
>> untouched. I think there is a trade-o
On Mon, Dec 09, 2013 at 01:24:36PM +0800, Fam Zheng wrote:
> VMFS extent line in description file should be with 4 fields:
>
> RW VMFS "file-name.vmdk"
>
> Check the number explicitly and report error if offset is appended as
> FLAT, which should be invalid format.
>
> Reported-by: Paolo Bo
Hi Mark,
this patch breaks booting with OBP:
Probing /iommu@0,1000/sbus@0,10001000 at 5,0 espdma esp sd st
SUNW,bpp ledma le
Probing /iommu@0,1000/sbus@0,10001000 at 4,0 SUNW,CS4231 power-management
Probing /iommu@0,1000/sbus@0,10001000 at 1,0 Nothing there
Probing /iommu@0,100
On Thu, Dec 19, 2013 at 5:10 PM, Edgar E. Iglesias
wrote:
> On Thu, Dec 19, 2013 at 04:37:22PM +1000, Peter Crosthwaite wrote:
>> On Thu, Dec 19, 2013 at 3:51 PM, wrote:
>> > From: "Edgar E. Iglesias"
>> >
>> > Signed-off-by: Edgar E. Iglesias
>> > ---
>> > hw/microblaze/petalogix_ml605_mmu.c
On Tue, Dec 17, 2013 at 08:00:00PM +0800, Fam Zheng wrote:
> @@ -1511,48 +1521,55 @@ static int vmdk_create_extent(const char *filename,
> int64_t filesize,
> header.check_bytes[3] = 0xa;
>
> /* write all the data */
> -ret = qemu_write_full(fd, &magic, sizeof(magic));
> -if (r
On 12/10/2013 07:16 PM, Alexey Kardashevskiy wrote:
> On 12/03/2013 02:30 PM, Alexey Kardashevskiy wrote:
>> Hi!
>>
>> This is some cleanup. Please, comment. Thanks!
>
>
> Ping, anyone?
Ping?
>
>
>> Changes:
>> v5:
>> * cleanup
>> * removed cpustate::kvm_cpu_id
>> * split into 2 patches -
Peter Maydell wrote:
> On 17 December 2013 15:26, Juan Quintela wrote:
>> @@ -399,8 +401,9 @@ static int
>> kvm_get_dirty_pages_log_range(MemoryRegionSection *section,
>> page_number = (i * HOST_LONG_BITS + j) * hpratio;
>> addr1 = page_number * TARGET_PAGE_SIZE;
On 12/19/2013 04:44 PM, Peter Crosthwaite wrote:
On Thu, Dec 19, 2013 at 9:38 PM, Peter Maydell wrote:
On 19 December 2013 07:27, Fedorov Sergey wrote:
Yes, this banking scheme makes state changing events quite heavy. But
maintaining the active copies allows to keep translation table walking
On Thu, Dec 19, 2013 at 7:03 PM, Peter Maydell wrote:
> On 19 December 2013 05:49, Christoffer Dall
> wrote:
>> On Thu, Nov 28, 2013 at 05:43:54PM +, Peter Maydell wrote:
>>> The other possibility is that it's a correct implementation
>>> of 11MPCore GIC semantics -- the documentation of the
On 19 December 2013 13:49, Peter Crosthwaite
wrote:
> On Thu, Dec 19, 2013 at 7:03 PM, Peter Maydell
> wrote:
>> My initial thought would be either to have if statements at the
>> relevant points (which is how we've handled 11mpcore
>> differences so far), or to bite the bullet and reflect the
>
On Thu, Dec 19, 2013 at 11:39 PM, Fedorov Sergey wrote:
>
> On 12/19/2013 04:44 PM, Peter Crosthwaite wrote:
>>
>> On Thu, Dec 19, 2013 at 9:38 PM, Peter Maydell
>> wrote:
>>>
>>> On 19 December 2013 07:27, Fedorov Sergey wrote:
Yes, this banking scheme makes state changing events quit
On 19 December 2013 14:01, Peter Crosthwaite
wrote:
> On Thu, Dec 19, 2013 at 11:39 PM, Fedorov Sergey
> wrote:
>> "Banked system control registers have two copies, one Secure and one
>> Non-secure."
>>
>
> Ok fair enough. I will wager though that sooner or later ARM will find
> a reason to bank
On Fri, Dec 13, 2013 at 05:22:08PM +0100, Igor Mammedov wrote:
> .. so it could be used for adding CPU hotplug to Q35 machine
>
> Signed-off-by: Igor Mammedov
Sounds good but please call this file cpu_hotplug.c/.h or cpu-hotplug.c/h
and make all prefixes acpi_cpu_hotplug and AcpiCpuHotplug.
>
On Fri, Dec 13, 2013 at 05:22:06PM +0100, Igor Mammedov wrote:
> Hardcoded GPE0 mask isn't really needed. Since GPE0_STS initialized
> with all bits cleared and only QEMU itself can set bits there (i.e.
> guest can only clear bits in it). So guest can't triger SCI
> by setting _STS & _EN bits and t
On Fri, Dec 13, 2013 at 05:22:10PM +0100, Igor Mammedov wrote:
> it fixes IRQ storm since guest isn't able to lower SCI IRQ
> after it has been handled when it clears GPE event.
>
> Signed-off-by: Igor Mammedov
Applied, thanks.
> ---
> hw/acpi/ich9.c | 1 +
> 1 file changed, 1 insertion(+)
>
On Fri, Dec 13, 2013 at 05:22:07PM +0100, Igor Mammedov wrote:
> ... and rename it into acpi_update_sci() since it changes
> SCI on only on PM registers status.
>
> Signed-off-by: Igor Mammedov
Applied, thanks.
> ---
> ---
> hw/acpi/core.c | 18 ++
> hw/acpi/ich9.c
On Fri, Dec 13, 2013 at 05:22:11PM +0100, Igor Mammedov wrote:
> .. including readonly 'cpu-hotplug-io-base' property
>
> Signed-off-by: Igor Mammedov
Is this documented in the Q35 spec? Could not find it there.
If this is our PV code like PIIX, then we need to document this
interface.
> ---
>
Il 18/12/2013 19:03, Andreas Färber ha scritto:
>> > @@ -61,7 +69,6 @@ static void ioapic_common_realize(DeviceState *dev,
>> > Error **errp)
>> > {
>> > IOAPICCommonState *s = IOAPIC_COMMON(dev);
>> > IOAPICCommonClass *info;
>> > -static int ioapic_no;
>> >
>> > if (ioapic_
On Thu, Dec 19, 2013 at 11:59 PM, Peter Maydell
wrote:
> On 19 December 2013 13:49, Peter Crosthwaite
> wrote:
>> On Thu, Dec 19, 2013 at 7:03 PM, Peter Maydell
>> wrote:
>>> My initial thought would be either to have if statements at the
>>> relevant points (which is how we've handled 11mpcore
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