On 28 June 2013 19:26, Paolo Bonzini wrote:
> The next patch will change qemu/tls.h to support more platforms, but at
> some performance cost. Declare cpu_single_env directly instead of using
> the tls.h abstractions.
>
> Signed-off-by: Paolo Bonzini
> ---
> exec.c | 10
On 28 June 2013 08:01, Rob Landley wrote:
> Now that the next kernel's about to come out, I'm trying to get my arm
> versatile image to work under qemu 1.5.0. The old kernel doesn't work, and
> the current vanilla kernel doesn't work. This change broke it.
>
> I'm testing current linux-git both wi
On Saturday 29 June 2013 00:12:17 you wrote:
> > As far as I know, autoreconf does not exist in the red
> > hat/fedora/centos world.
> >
> > Can't find a yum, rpm. or other distro for it on the above os.
>
> You aren't looking very hard; on my RHEL 6.4 box (which has the same
> packages as what
On Friday 28 June 2013 18:20:29 you wrote:
> autoreconf is part of the autoconf package. Do you have that installed?
>
Hi,
Thanks for the response.
You're right, it was the lack of autoconf. Actually, on CentOS/RH, you need
to check for
autoconf
automake (includes autoconf?)
libtools
See
Am 28.06.2013 13:59, schrieb Andre Przywara:
> From: Rob Herring
>
> While the Calxeda Midway part is actually a bit more than a "Highbank
> with A15s", for QEMU's purposes this view is sufficient. So to allow
> both emulation with that chip as well as KVM guests using that model
> add an A15 CPU
Am 28.06.2013 19:35, schrieb Richard Henderson:
> On 06/28/2013 06:22 AM, Peter Maydell wrote:
>> The functions cpu_clone_regs() and cpu_set_tls() are not purely CPU
>> related -- they are specific to the TLS ABI for a a particular OS.
>> Move them into the linux-user/ tree where they belong.
>>
>>
Am 28.06.2013 19:32, schrieb Richard Henderson:
> On 06/28/2013 06:23 AM, Andreas Färber wrote:
>> A transition from CPUFooState to FooCPU can be considered safe,
>> just like FooCPU::env access in the opposite direction.
>> The only benefit of the FOO_CPU() casts would be protection against
>> bog
Am 29.06.2013 14:54, schrieb Andreas Färber:
> Am 28.06.2013 13:59, schrieb Andre Przywara:
>> From: Rob Herring
>>
>> While the Calxeda Midway part is actually a bit more than a "Highbank
>> with A15s", for QEMU's purposes this view is sufficient. So to allow
>> both emulation with that chip as w
On PPC64 systems MSI Messages are translated to system IRQ in a PCI
host bridge. This is already supported for emulated MSI/MSIX but
not for irqfd where the current QEMU allocates IRQ numbers from
irqchip and maps MSIMessages to those IRQ in the host kernel.
The patch extends irqfd support in orde
i686-w64-mingw32-gcc (GCC) 4.6.3 from Debian wheezy reports these warnings:
hw/ppc/spapr_hcall.c:188:1: warning:
control reaches end of non-void function [-Wreturn-type]
hw/ppc/spapr_pci.c:454:1: warning:
control reaches end of non-void function [-Wreturn-type]
Both warnings are fixed by using
File mapping may fail with EACCES.
Signed-off-by: Jürg Billeter
---
linux-user/mmap.c | 4
1 file changed, 4 insertions(+)
diff --git a/linux-user/mmap.c b/linux-user/mmap.c
index b412e3f..de22197 100644
--- a/linux-user/mmap.c
+++ b/linux-user/mmap.c
@@ -483,6 +483,10 @@ abi_long target_m
Fix following bugs in "fallback implementation of counting semaphores
with mutex+condvar" added in c166cb72f1676855816340666c3b618beef4b976:
- waiting threads are not restarted properly if more than one threads
are waiting unblock signals in qemu_sem_timedwait()
- possible missing pthread_cond
Am 29.06.2013 15:45, schrieb Alexey Kardashevskiy:
> On PPC64 systems MSI Messages are translated to system IRQ in a PCI
> host bridge. This is already supported for emulated MSI/MSIX but
> not for irqfd where the current QEMU allocates IRQ numbers from
> irqchip and maps MSIMessages to those IRQ i
On Sat, Jun 29, 2013 at 8:45 AM, Alexey Kardashevskiy wrote:
> On PPC64 systems MSI Messages are translated to system IRQ in a PCI
> host bridge. This is already supported for emulated MSI/MSIX but
> not for irqfd where the current QEMU allocates IRQ numbers from
> irqchip and maps MSIMessages to
On Sat, Jun 29, 2013 at 03:47:26PM +0200, Stefan Weil wrote:
> i686-w64-mingw32-gcc (GCC) 4.6.3 from Debian wheezy reports these warnings:
>
> hw/ppc/spapr_hcall.c:188:1: warning:
> control reaches end of non-void function [-Wreturn-type]
>
> hw/ppc/spapr_pci.c:454:1: warning:
> control reaches
Am 27.06.2013 09:38, schrieb Xu Wang:
> From: Xu Wang
>
> If user creates a image with loop in backing file, qemu doesn't give any
> warning or error report and creation successful. If this image was opend
> by qemu, no response would occure and segment fault would happend at last.
> Hence these
The current code includes assert.h very early (from qemu-common.h),
so the definition of NDEBUG was without any effect.
In the initial version from 2004, NDEBUG was used to disable the assertions.
Those assertions are not in time critical code, so it is no longer
reasonable to disable them and the
We can tell the guest the frequency of its time base through fwcfg.
However, we tell it a different value from the speed tb actually runs
at. Let's fix it and make the tbfreq initialization and the fwcfg exposure
use the same values.
Signed-off-by: Alexander Graf
---
hw/ppc/mac_newworld.c | 5 +
The bug is still present in the newly released QEMU-1.5.1. I've ported
Chalkerx's patch to this release as well. See attached patch.
Is there a problem with this patch, since it has not been committed?
// MOKI
** Patch added: "patch-qemu-1.5.1-fpip.diff"
https://bugs.launchpad.net/qemu/+bug/
Am 29.06.2013 19:10, schrieb Morten Shearman Kirkegaard:
> The bug is still present in the newly released QEMU-1.5.1. I've ported
> Chalkerx's patch to this release as well. See attached patch.
>
> Is there a problem with this patch, since it has not been committed?
>
> // MOKI
>
> ** Patch adde
On 06/28/2013 02:43 PM, Alexander Graf wrote:
On 28.06.2013, at 14:11, Mian M. Hamayun wrote:
diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
index c614070..4df5292 100644
--- a/linux-headers/linux/kvm.h
+++ b/linux-headers/linux/kvm.h
@@ -783,6 +783,7 @@ struct kvm_dirty_tl
Thanks for porting the patch.
This is the mailing thread I started back in 2010 with that patch:
http://lists.gnu.org/archive/html/qemu-devel/2010-11/msg02497.html
That thread has some problems noted.
Sadly, I did not have enough free time to investigate all the other
places that should be fixed
How is one meant to make the tests? make test fails with:
make[1]: Entering directory `/home/amb/qemu/git/qemu/tests/tcg'
cc -m32 -I/home/amb/qemu/git/qemu/tcg -I/home/amb/qemu/git/qemu/tcg/i386
-I/home/amb/qemu/git/qemu/linux-headers
-I/home/amb/qemu/git/qemu/linux-headers -I. -I/home/amb/qemu
This is an RFC for a very lightly tested patch.
Add a delay option to blkdebug, allowing operations to be delayed by
a specifiable number of microseconds. Example configuration:
[inject-error]
event = "read_aio"
delay = "20"
Signed-off-by: Alex Bligh
---
block/blkdebug.c | 83 ++
1 fi
On 29.06.2013, at 19:48, Mian M. Hamayun wrote:
>
> On 06/28/2013 02:43 PM, Alexander Graf wrote:
>> On 28.06.2013, at 14:11, Mian M. Hamayun wrote:
>>
>>> diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
>>> index c614070..4df5292 100644
>>> --- a/linux-headers/linux/kvm.h
>>
On 28 June 2013 13:11, Mian M. Hamayun wrote:
> From: "Mian M. Hamayun"
>
> The init function tries to initialize with Foundation models first and on
> failure retries initializing on Fast Models.
>
> Get and Put Registers deal with the basic state of Aarch64 CPUs for the
> moment.
>
> Signed-of
On 28 June 2013 13:11, Mian M. Hamayun wrote:
> From: "Mian M. Hamayun"
>
> Signed-off-by: Mian M. Hamayun
> ---
> configure |3 +-
> default-configs/aarch64-softmmu.mak | 83
> +++
> 2 files changed, 85 insertions(+), 1 deletion(
On 28 June 2013 13:11, Mian M. Hamayun wrote:
> From: "Mian M. Hamayun"
>
> The vexpress model for A57 is based on the A15 machine model with a few
> changes in the daughterboard initialization (using a subset of A15
> functionality). The A57 daughterboard init also shares the A15MPCore
> private
On 28 June 2013 13:11, Mian M. Hamayun wrote:
> From: Alexander Spyridakis
>
> AArch64 uses a cpu-release-addr memory location (defined in the dts) as
> a way to inform secondary CPUs where to jump to and enter their holding
> pen. Inject a very simple bootloader that polls this memory location,
Hello,
This series cleans up gdbstub by changing all its internal CPU state to CPUState
and by moving most target-specific code into the target directories.
It depends on part 10 and starts with a follow-up, consolidating reset logging.
Support for m68k, moxie and unicore32 to set the PC via gdb
This adds support for GDB's c addr (Continue) and s addr (Single Step).
Prepares for dropping cpu_pc_from_tb().
Signed-off-by: Andreas Färber
---
target-m68k/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c
index 1b6ef66..1ac1893 100644
---
This adds support for GDB's c addr (Continue) and s addr (Single Step).
Prepares for dropping cpu_pc_from_tb().
Signed-off-by: Andreas Färber
---
target-unicore32/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c
index 6572f01..2e9
Since first_cpu/next_cpu are CPUState, CPUArchState is no longer needed.
Signed-off-by: Andreas Färber
---
gdbstub.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index 5793bcd..4a0d04e 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -289,7 +289,7 @
x86 was using additional CPU_DUMP_* flags, so make that configurable in
CPUClass::reset_dump_flags.
This adds reset logging for alpha, unicore32 and xtensa.
Signed-off-by: Andreas Färber
---
include/qom/cpu.h | 2 ++
qom/cpu.c | 8
target-arm/cpu.c
This adds support for GDB's c addr (Continue) and s addr (Single Step).
Prepares for dropping cpu_pc_from_tb().
Signed-off-by: Andreas Färber
---
target-moxie/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c
index 92ca594..8e32584 100644
Since commit 878096eeb278a8ac1ccd6667af73e026f29b4cf5 (cpu: Turn
cpu_dump_{state,statistics}() into CPUState hooks) CPUArchState is no
longer needed.
Add documentation and make the functions available through qemu/log.h
outside NEED_CPU_H to allow use in qom/cpu.c. Moving them to qom/cpu.h
was not
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-arm/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index af2aef2..9310c58
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-sparc/translate.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index eb6e800..
Since commit cb446ecab714b2444a270be209e0533bcd2ee534 (kvm: Change
cpu_synchronize_state() argument to CPUState), one was no longer
accessing CPUArchState, the other was just checking existence.
Signed-off-by: Andreas Färber
---
gdbstub.c | 10 +-
1 file changed, 5 insertions(+), 5 delet
Where no extra implementation is needed, fall back to CPUClass::set_pc().
Signed-off-by: Andreas Färber
---
cpu-exec.c | 8 +++-
include/exec/exec-all.h | 3 ---
include/qemu/typedefs.h | 3 +++
include/qom/cpu.h | 1 +
target-alpha/cpu.h | 5 -
target-arm/cp
Use CPUState::env_ptr for now.
Needed for GdbState::c_cpu.
Signed-off-by: Andreas Färber
---
exec.c | 4 ++--
gdbstub.c | 9 +
include/exec/cpu-all.h | 6 --
include/qom/cpu.h | 6 ++
4 files changed, 13 insertions(+), 12 deletions(-)
diff --gi
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-m68k/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 3752094..2d73a
CPUArchState is no longer directly used since converting CPU loops to
CPUState.
Prepares for changing GDBState::c_cpu to CPUState.
Signed-off-by: Andreas Färber
---
gdbstub.c| 12
include/sysemu/kvm.h | 4 ++--
kvm-all.c| 10 --
kvm-stub.c
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-i386/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 14b0298..6550c
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-mips/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 160c0c0..8246c
Use CPUState::env_ptr for now.
Prepares for changing GDBState::g_cpu to CPUState.
Signed-off-by: Andreas Färber
---
gdbstub.c | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index a8fafe2..cee9c13 100644
--- a/gdbstub.c
+++ b/gdbstub.c
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-sh4/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 292c9e9..2fbe668
Needed for moving singlestep_enabled to CPUState.
Signed-off-by: Andreas Färber
---
target-alpha/translate.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index dd7f0fb..147285a 100644
--- a/target-alpha/translate.
Callback implementations were specific to arm and m68k, so can easily
cast to ARMCPU and M68kCPU respectively.
Prepares for changing GDBState::c_cpu to CPUState.
Signed-off-by: Andreas Färber
---
gdbstub.c | 2 +-
include/exec/gdbstub.h | 2 +-
target-arm/arm-semi.c | 8 ++-
Use UniCore32CPU and bool.
Prepares for moving singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-unicore32/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index e1fe
Signed-off-by: Andreas Färber
---
gdbstub.c | 7 +++
include/exec/gdbstub.h | 2 +-
target-arm/helper.c | 7 ---
target-m68k/helper.c| 3 ++-
target-ppc/translate_init.c | 15 ---
5 files changed, 18 insertions(+), 16 deletions(-)
di
Prepares for changing cpu_single_step() argument to CPUState.
Signed-off-by: Andreas Färber
---
cpu-exec.c| 2 +-
cpus.c| 2 +-
exec.c| 10 ++
include/exec/cpu-defs.h | 1 -
include/qom/cpu.h | 1 +
In particular reindent to 4 instead of 2 spaces.
Prepares for changing cpu_single_step() argument in gdb_handlesig().
Signed-off-by: Andreas Färber
---
gdbstub.c | 94 +++
1 file changed, 47 insertions(+), 47 deletions(-)
diff --git a
Prepares for changing GDBState::c_cpu to CPUState.
Signed-off-by: Andreas Färber
---
bsd-user/main.c| 10 ++
gdbstub.c | 6 +++---
include/exec/gdbstub.h | 2 +-
linux-user/main.c | 35 +++
linux-user/signal.c| 3 ++-
5 fil
Make inline target_memory_rw_debug() always available and change its
argument to CPUState. Let it check if CPUClass::memory_rw_debug provides
a specialized callback and fall back to cpu_memory_rw_debug() otherwise.
The only overriding implementation is for 32-bit sparc.
This prepares for changing
Prepares for changing gdb_register_coprocessor() argument to CPUState.
Signed-off-by: Andreas Färber
---
gdbstub.c | 11 ++-
include/exec/cpu-defs.h | 2 --
include/qom/cpu.h | 1 +
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
Also use bool argument while at it.
Prepares for replacing DisasContext::env with CPUState and for moving
singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-alpha/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-alpha/tr
Propagate X86CPU in kvmvapic for simplicity.
Signed-off-by: Andreas Färber
---
cpus.c | 4 +--
disas.c | 4 +--
exec.c | 6 ++--
gdbstub.c | 2 +-
hw/i386/kvmvapic.c | 72 +++-
Since all targets now assign a softmmu-only field, we can drop helpers
cpu_class_set_{do_unassigned_access,vmsd}() and device_class_set_vmsd().
Prepares for changing cpu_memory_rw_debug() argument to CPUState.
Signed-off-by: Andreas Färber
---
exec.c | 20 ++--
hw/i
Register a CPU type per core registered. Save the XtensaConfig in
XtensaCPUClass instead of CPUXtensaState.
Prepares for storing per-class GDB register count.
Signed-off-by: Andreas Färber
---
gdbstub.c | 17 ---
hw/xtensa/pic_cpu.c | 47 --
target-xt
On 28/06/2013 23:44, Mark Cave-Ayland wrote:
On 28/06/13 03:08, Rob Landley wrote:
Commit 467b34689d27 upgraded the openbios image, and ever since my linux
system images hang about the time they try to initialize interrupts.
http://landley.net/aboriginal/bin/system-image-sparc.tar.bz2
Extract
This moves setting the Program Counter from gdbstub into target code.
Use uint64_t type as maximum replacement for target_ulong.
Signed-off-by: Andreas Färber
---
gdbstub.c | 39 ++-
include/qom/cpu.h | 1 +
target-alpha/cpu.c
Use MicroBlazeCPU and bool.
Prepares for moving singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-microblaze/translate.c | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
in
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-cris/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 09d0d2b..ce1f0
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-xtensa/translate.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index dcb90a
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-lm32/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index 227a801..6d107
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-ppc/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 3643863..eb96272
Allows us to drop find_cpu().
Xtensa still needs env for its num_g_regs.
Signed-off-by: Andreas Färber
---
gdbstub.c | 68 +--
1 file changed, 31 insertions(+), 37 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index 81a8941..a8fafe2
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Signed-off-by: Andreas Färber
---
target-s390x/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index cd9880e..cb
Use CPUState::env_ptr for Xtensa.
This removes the last user of CPUArchState from gdb_set_stop_cpu().
Signed-off-by: Andreas Färber
---
gdbstub.c | 35 +++
1 file changed, 15 insertions(+), 20 deletions(-)
diff --git a/gdbstub.c b/gdbstub.c
index fa44550..7be234
As a side effect this should fix coprocessor register numbering for SMP.
Signed-off-by: Andreas Färber
---
gdbstub.c | 80 ++---
include/qom/cpu.h | 3 ++
qom/cpu.c | 9 +
target-alpha/cpu.c | 1
On 06/30/2013 12:28 AM, Anthony Liguori wrote:
> On Sat, Jun 29, 2013 at 8:45 AM, Alexey Kardashevskiy wrote:
>> On PPC64 systems MSI Messages are translated to system IRQ in a PCI
>> host bridge. This is already supported for emulated MSI/MSIX but
>> not for irqfd where the current QEMU allocates
On 6/28/13 14:01 , "Laszlo Ersek" wrote:
>On 06/06/13 17:06, Tomoki Sekiyama wrote:
>
>> diff --git a/qga/vss-win32-requester.h b/qga/vss-win32-requester.h
>> new file mode 100644
>> index 000..f180f56
>> --- /dev/null
>> +++ b/qga/vss-win32-requester.h
...
>>+HRESULT vss_init(void);
>
>Can yo
On a real G3 Beige the secondary IDE bus lives on the mac-io chip, not
on some random PCI device. Move it there to become more compatible.
While at it, also clean up the IDE channel connection logic.
Signed-off-by: Alexander Graf
---
v1 -> v2:
- fix IRQ mapping
---
hw/ide/macio.c|
The DBDMA engine really is running all the time, waiting for input. However
we don't want to waste cycles constantly polling.
So introduce a kick function that data providers can call to notify the
DBDMA controller of new input.
Signed-off-by: Alexander Graf
---
hw/misc/macio/mac_dbdma.c | 5 +
We can tell the guest the frequency of its time base through fwcfg.
However, we tell it a different value from the speed tb actually runs
at. Let's fix it and make the tbfreq initialization and the fwcfg exposure
use the same values.
Signed-off-by: Alexander Graf
---
hw/ppc/mac_newworld.c | 5 +
Recently there has been a lot of progress on the OpenBIOS side to get Mac OS X
to boot.
For a while now it seemed there was only very little to make it a fully working
guest os in QEMU.
This patch set is the result of this. With this I can successfully boot Mac OS X
10.2 to 10.4 with the g3beige
s/^I//g on the file.
Signed-off-by: Alexander Graf
---
hw/ide/macio.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
index 7a1c573..82409dc 100644
--- a/hw/ide/macio.c
+++ b/hw/ide/macio.c
@@ -55,7 +55,7 @@ static void pmac_ide
The macio code is basically undebuggable as it stands today, with no
debug prints anywhere whatsoever. DBDMA was better, but I needed a
few more to create reasonable logs that tell me where breakage is.
Add a DPRINTF macro in the macio source file and add a bunch of debug
prints that are all disab
There was a debug print that didn't compile for me because the format
and the arguments weren't in sync. Fix it up.
Signed-off-by: Alexander Graf
---
hw/misc/macio/mac_dbdma.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_dbdm
The DBDMA engine really just reads bytes from a producing device (IDE
in our case) and shoves these bytes into memory. It doesn't care whether
any alignment takes place or not.
Our code today however assumes that block accesses always happen on
sector (512 byte) boundaries. This is a fair assumpti
Soon we will introduce intermediate processing pauses which will
allow the bottom half to restart a DMA request that couldn't be
fulfilled yet.
For that to work, move the processing variable into the io struct
which is what DMA providers work with.
Signed-off-by: Alexander Graf
---
hw/misc/maci
The DBDMA controller has a bottom half to asynchronously process DMA
request queues.
This bh was stored as a gross static variable. Move it into the device
struct instead.
While at it, move all users of it to the new generic kick function.
Signed-off-by: Alexander Graf
---
hw/misc/macio/mac_db
The DBDMA controller can not change its command stream while it's
actively streaming data, true. But the fact that it's in RUN state
doesn't actually indicate anything. It could just as well be in
WAIT while in RUN. And then it's legal to change commands.
This fixes a real world issue I've encount
We should only start processing DMA requests when we have data to process.
Hold off working through the DMA shuffling until the IDE core told us that
it's ready.
This is required because the guest can program the DMA engine or the IDE
transfer first. Both are legal.
Signed-off-by: Alexander Graf
We usually keep struct and constant definitions in header files. Move
them there to stay consistent and to make access to fields easier.
Signed-off-by: Alexander Graf
---
hw/misc/macio/mac_dbdma.c | 117
include/hw/ppc/mac_dbdma.h | 118 +
s/^I//g on the file with a few manual tweaks to align things.
Signed-off-by: Alexander Graf
---
hw/misc/macio/mac_dbdma.c | 102 +++---
1 file changed, 51 insertions(+), 51 deletions(-)
diff --git a/hw/misc/macio/mac_dbdma.c b/hw/misc/macio/mac_db
We need to know when the IDE core starts a DMA transfer. Add a notifier
function so we have the chance to start transmitting data.
Signed-off-by: Alexander Graf
---
hw/ide/macio.c | 40
hw/ppc/mac.h | 2 ++
2 files changed, 42 insertions(+)
diff --git
From: Hervé Poussineau
IABR SPR is already registered in gen_spr_603(), called from init_proc_603E().
Signed-off-by: Hervé Poussineau
Reviewed-by: Andreas Färber
Signed-off-by: Alexander Graf
---
target-ppc/translate_init.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/target-ppc/t
The current logic updates KVM's view of our interrupt map every time we
change it. While this is nice and bullet proof, it slows things down
badly for me. QEMU spends about 3 seconds on every start telling KVM what
news it has on its routing maps.
Instead, let's just synchronize the whole irq rout
From: Fabien Chouteau
On PPC 6xx, data and code have separated TLBs. Until now QEMU was only
looking at data TLBs, which is not good when GDB wants to read code.
This patch adds a second call to get_physical_address() with an
ACCESS_CODE type of access when the first call with ACCESS_INT fails.
On PPC, we can have different types of interrupt controllers, so we really
only know that we are going to use one when we created it.
Export kvm_init_irq_routing() to common code, so that we don't have to call
kvm_irqchip_create().
Signed-off-by: Alexander Graf
---
include/sysemu/kvm.h | 1 +
k
The usual MSI injection mechanism writes msi.data into memory using an
le32 wrapper. So on big endian guests, this swaps msg.data into the
expected byte order.
For irqfd however, we don't swap the payload right now, rendering
in-kernel MPIC emulation broken on PowerPC.
Swap msg.data to the correc
On PPC, we don't support MP state. So far it's not necessary and I'm
not convinced yet that we really need to support it ever.
However, the current idle logic in QEMU assumes that an in-kernel PIC
also means we support MP state. This assumption is not true anymore.
Let's split up the two cases in
Hi Blue / Aurelien,
This is my current patch queue for ppc. Please pull.
Alex
The following changes since commit ffeec223b55ea696567ed544016824199cd7c7bc:
Merge remote-tracking branch 'mjt/trivial-patches' into staging (2013-06-28
15:48:35 -0500)
are available in the git repository at:
From: Andreas Färber
6544 -> 8544
Signed-off-by: Andreas Färber
Signed-off-by: Alexander Graf
---
hw/ppc/mpc8544_guts.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/mpc8544_guts.c b/hw/ppc/mpc8544_guts.c
index 193beab..98540a4 100644
--- a/hw/ppc/mpc8544_guts.c
+
Mac OS X expects the uninorth control register set to contain one
register that always reads back what it writes in. Expose that.
This is just a temporary hack. Eventually, we want to expose the
uninorth (/uni-n in device tree) as a separate QOM device.
Signed-off-by: Alexander Graf
---
hw/ppc/
There are cases where a kvm provided function is called from generic
hw code that doesn't know whether kvm is available or not. Provide
a stub file which can provide simple replacement functions for those
cases.
Signed-off-by: Alexander Graf
Reviewed-by: Paolo Bonzini
---
target-ppc/Makefile.ob
The L2CR register contains a number of bits that either impose configuration
which we can't deal with or mean "something is in progress until the bit is
0 again".
Since we don't model the former and we do want to accomodate guests using the
latter semantics, let's just ignore writes to L2CR. That
1 - 100 of 133 matches
Mail list logo
