On 01/20/2012 11:05 AM, Peter Maydell wrote:
> Support passing a board ID value to the kernel in r1
> that is more than 16 bits wide. This is needed to pass
> the '-1 == invalid' value for boards which only support
> device tree booting.
>
> Signed-off-by: Peter Maydell
> ---
> This applies after
On Fri, Jan 20, 2012 at 09:09:46AM +, Peter Maydell wrote:
> On 20 January 2012 06:12, 陳韋任 wrote:
> > Out of curiosity. What's ARM memory model? From the Wikipedia [1], it seems
> > ARMv7 has the same memory model as IA64.
>
> The ARM memory model is the set of semantics for memory
> accesse
From: Jan Kiszka
All LVTs are masked on reset, so the timer becomes ineffective. Letting
it tick nevertheless is harmless, but will at least create a spurious
trace event.
Signed-off-by: Jan Kiszka
---
hw/apic.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/hw/apic.
Accroding to my experience, you list all the case already.
Regards,
chenwj
From: Jan Kiszka
Split up the IOAPIC analogously to APIC and i8259. KVM will share the
IOAPICCommonState, the vmstate, reset logic and certain init parts with
the user space model.
Signed-off-by: Jan Kiszka
---
Makefile.target |2 +-
hw/ioapic.c | 130 ++-
From: Vadim Rozenfeld
[Jan: fix build with CONFIG_USER_ONLY]
Signed-off-by: Marcelo Tosatti
---
Makefile.target |2 +
target-i386/cpuid.c | 14 +++
target-i386/hyperv.c | 64 ++
target-i386/hyperv.h | 43 ++
From: Jan Kiszka
More KVM-specific devices will come, so let's start with moving the
kvmclock into a dedicated folder.
Signed-off-by: Jan Kiszka
---
Makefile.target |4 +-
configure |1 +
hw/kvm/clock.c | 120 +++
hw/kvm/clock
From: Jan Kiszka
Add the basic infrastructure to active in-kernel irqchip support, inject
interrupts into these models, and maintain IRQ routes.
Routing is optional and depends on the host arch supporting
KVM_CAP_IRQ_ROUTING. When it's not available on x86, we looe the HPET as
we can't route GSI
From: Jan Kiszka
Use DeviceState instead of PicState in the public i8259 API. This is
cleaner and allows to reorganize the PIC data structures for KVM reuse.
Signed-off-by: Jan Kiszka
---
hw/i8259.c | 17 +++--
hw/pc.h|7 +++
2 files changed, 14 insertions(+), 10 dele
From: Jan Kiszka
On real hardware, NMI button events are injected via the LINT1 line of
the APICs. E.g. kdump expect this wiring and gets upset if the per-APIC
LINT1 mask is not respected, i.e. if NMIs are injected to VCPUs that
should not receive them. Change the APIC emulation code to reflect t
From: Anthony PERARD
Do not allocate RAM during INMIGRATE runstate.
Do not actually "do" set_memory during migration.
Signed-off-by: Anthony PERARD
Signed-off-by: Stefano Stabellini
---
xen-all.c | 16
1 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/xen-all.
From: Jan Kiszka
Introduce a memory region type that can reserve I/O space. Such regions
are useful for modeling I/O that is only handled outside of QEMU, i.e.
in the context of an accelerator like KVM.
Any access to such a region from QEMU is a bug, but could theoretically
be triggered by guest
From: Jan Kiszka
Analogously to the APIC, we will reuse some parts of the user space
i8259 model for KVM. The base class provides a common device state, the
vmstate, the property list, a reset core and some shared init bits.
This also introduces a common helper to instantiate a single i8259 chip
On Mon, Jan 02, 2012 at 07:11:41AM -0500, Xin Tong wrote:
> In qemu, there is a virtual pc hash table and a physical pc hash
> table. virtual pc hash table is used to find tbs until a context
> switch. and physical pc hash table keeps all the translated tb.
> virtual pc hash table is smaller, acces
On 01/19/2012 09:17 PM, Alexander Graf wrote:
> E500mc supports IVORs 36-41. Add them to the support mask.
>
> Signed-off-by: Alexander Graf
> ---
> target-ppc/translate_init.c |6 +-
> 1 files changed, 5 insertions(+), 1 deletions(-)
>
> diff --git a/target-ppc/translate_init.c b/targe
On 01/20/2012 10:58 AM, Peter Maydell wrote:
> On 20 January 2012 16:57, Mark Langsdorf wrote:
>> On 01/20/2012 10:27 AM, Peter Maydell wrote:
>>> It's still not clear to me from this conversation if the right
>>> answer is "0", "-1" or "anything that's not a valid board ID
>>> and not -1 either".
On 01/19/2012 09:17 PM, Alexander Graf wrote:
> The e500 CPUs don't use 440's msync which falls on the same opcode IDs,
> but instead use the real powerpc sync instruction. This is important,
> since the invalid mask differs between the two.
Could you rename 4xx msync to explicitly be 4xx msync, i
Peter Maydell wrote:
> > "guest binaries don't actually rely that much on the memory model."
> >
> > I think the reason is those guest binaries are single thread. Memory model
> > is
> > important in multi-threaded case. BTW, our binary translator now can
> > translate
> > x86 binary to ARM bina
On 01/20/2012 01:30 AM, Kevin Wolf wrote:
>>> +++ b/hmp-commands.hx
>> Looking at this from libvirt's perspective, would it be possible to give
>> this a different name? Then libvirt would know that if
>> block_job_cancel_async exists, we have the official semantics; and if it
>> doesn't exist,
On 01/20/2012 07:21 AM, Alexander Graf wrote:
> When setting a TLB entry, we need to check if the TLB we're putting it in
> actually supports the given size. According to the 2.06 PowerPC ISA, a
> value that's out of range results in the minimum page size for the TLB
> to be used.
The ISA says, "I
On 01/19/2012 09:17 PM, Alexander Graf wrote:
> +case 3:
> +/* flush by pid and ea */
> +for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
> +int ways = booke206_tlb_ways(env, i);
> +
> +for (j = 0; j < ways; j++) {
> +tlb = booke206_get_tlbm(env,
This patch series adds support for the Calxeda Highbank SoC.
Makefile.target |2 +
hw/arm-misc.h | 17 ++
hw/arm_boot.c | 65 ++--
hw/highbank.c | 331
hw/ide/ahci.c | 44 ++
hw/xgmac.c | 421 +++
Long term, the config_base_register will be a QDM parameter. In the
meantime, models that use it need to be able to preserve it across
cpu_reset() calls.
Signed-off-by: Mark Langsdorf
---
Changes from v1-v12
Skipped
target-arm/helper.c |7 +++
1 files changed, 7 insertions(+), 0
From: Rob Herring
This adds very basic support for the xgmac ethernet core. Missing things
include:
- statistics counters
- WoL support
- rx checksum offload
- chained descriptors (only linear descriptor ring)
- broadcast and multicast handling
Signed-off-by: Rob Herring
Signed-off-by: Mark La
From: Rob Herring
Adds support for Calxeda's Highbank SoC.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Changes from v12
Reverted board_id to -1. Added comments clarifying why this is legal.
Changes from v11
Provided a meaningful board ID
Added comments
From: Peter Maydell
Support passing a board ID value to the kernel in r1
that is more than 16 bits wide. This is needed to pass
the '-1 == invalid' value for boards which only support
device tree booting.
Signed-off-by: Peter Maydell
Tested-by: Mark Langsdorf
---
Changes from v1-v12
Sk
Create two functions, write_secondary_boot() and secondary_cpu_reset_hook(),
to allow platforms more control of how secondary CPUs are brought up. The
new functions default to NULL and aren't called unless they are populated
so there are no changes to existing platform models.
Signed-off-by: Mark
From: Rob Herring
Add support for ahci on sysbus.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Reviewed-by: Andreas Färber
---
Changes from v10-v12
None
Changes from v9
Changed typedef struct names to CamelCase
Changes from v7, v8
None
Changes from v5, v6
On 01/05/2012 04:00 PM, Michael S. Tsirkin wrote:
Just chmod /dev/vhost-net to allow access
I wonder whether it's considered a security risk to allow non-root
users access to /dev/vhost-net?
(Or is there a way to have root prepare limited use of vhost for only
some users or some network device
Adding to my symptom description: I re-tested with "vhost=on" in addition
and verified this feature was actually used.
But this didn't change the benchmark results.
Regards,
Lutz Vieweg
On 01/20/2012 04:10 PM, Lutz Vieweg wrote:
Hi,
I've been using qemu-kvm along with ordinary tap-devices and
陳韋任 wrote:
> What's load/store exclusive implementation?
It's how some architectures do atomic operations, instead of having
atomic instructions like x86 does.
> And as a general emulator, QEMU shouldn't implement any
> architecture-specific memory model, right? What comes into my mind
> is QEM
The __attribute__((constructor)) init_main_loop() automatically get
called if qemu-tool.o is linked in. On win32, this leads to
a qemu_notify_event() call which attempts to SetEvent() on a HANDLE that
won't be initialized until qemu_init_main_loop() is manually called,
breaking qemu-tools.o program
On 20 January 2012 19:25, Mark Langsdorf wrote:
> It looks like there's an issue with commit 2be276242135eac6,
> in that target-arm/helper.c:cpu_reset() is called after
> hw/highbank.c:highbank_cpu_reset() and keeps clobbering
> our c15_config_base_address.
You may recall that when you first sent
On 20 January 2012 20:43, Grant Likely wrote:
> On Fri, Jan 20, 2012 at 11:43 AM, Grant Likely
> wrote:
>> From: Jeremy Kerr
>>
>> Signed-off-by: Jeremy Kerr
>> Cc: Paul Brook
>> Cc: Peter Maydell
>> Cc: Rob Herring
>> Signed-off-by: Grant Likely
>
> Oops, this one won't apply directly sinc
On 20 January 2012 18:27, Grant Likely wrote:
> On Fri, Jan 20, 2012 at 01:57:29PM +, Peter Maydell wrote:
>> I wonder if we should be passing in anything-except-minus-1,
>> since if you pass -1 and no DT then the kernel will fail
>> silently, whereas if you pass something else and no DT the
>
Am 20.01.2012 um 21:01 schrieb Scott Wood :
> On 01/20/2012 07:21 AM, Alexander Graf wrote:
>> When setting a TLB entry, we need to check if the TLB we're putting it in
>> actually supports the given size. According to the 2.06 PowerPC ISA, a
>> value that's out of range results in the minimum p
On 20.01.2012, at 21:40, Scott Wood wrote:
> On 01/19/2012 09:17 PM, Alexander Graf wrote:
>> +case 3:
>> +/* flush by pid and ea */
>> +for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
>> +int ways = booke206_tlb_ways(env, i);
>> +
>> +for (j = 0; j < ways; j
On 20.01.2012, at 20:16, Scott Wood wrote:
> On 01/19/2012 09:17 PM, Alexander Graf wrote:
>> E500mc supports IVORs 36-41. Add them to the support mask.
>>
>> Signed-off-by: Alexander Graf
>> ---
>> target-ppc/translate_init.c |6 +-
>> 1 files changed, 5 insertions(+), 1 deletions(-)
>>
Nobody needs to run bamboo in 0.12 compat mode. Remove the machine.
Signed-off-by: Alexander Graf
---
hw/ppc440_bamboo.c | 22 +-
1 files changed, 1 insertions(+), 21 deletions(-)
diff --git a/hw/ppc440_bamboo.c b/hw/ppc440_bamboo.c
index c17f6f7..84e45b4 100644
--- a/hw/p
From: Andreas Färber
Signed-off-by: Andreas Färber
Signed-off-by: Alexander Graf
---
MAINTAINERS |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index f7fc2ba..87237a6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -301,6 +301,7 @@ L: qemu-...@
The msync instruction as defined today is only valid on 4xx cores, not
on e500 which also supports msync, but treats it the same way as sync.
Rename it to reflect that it's 4xx only.
Signed-off-by: Alexander Graf
---
target-ppc/translate.c |4 ++--
1 files changed, 2 insertions(+), 2 deleti
The separation of ppc440 and ppc440_bamboo makes some sense, since ppc440
is the SoC while ppc440_bamboo is the actual board. But the separation
makes things harder for us for no good reason, so let's just fold them
in together with each other.
Signed-off-by: Alexander Graf
---
Makefile.target
The e500 CPUs don't use 440's msync which falls on the same opcode IDs,
but instead use the real powerpc sync instruction. This is important,
since the invalid mask differs between the two.
Signed-off-by: Alexander Graf
---
target-ppc/translate.c |3 +--
target-ppc/translate_init.c |
From: Benjamin Herrenschmidt
The virtio config area in PIO space is a bit special. The initial
header is little endian but the rest (device specific) is guest
native endian.
The PIO accessors for PCI on machines that don't have native IO ports
assume that all PIO is little endian, which works fi
Our code only knows IVORs up to 37. Add the new ones defined in ISA 2.06
from 38 - 42.
Signed-off-by: Alexander Graf
Reviewed-by: Andreas Färber
---
target-ppc/cpu.h|5 +
target-ppc/translate_init.c | 29 +++--
2 files changed, 20 insertions(+), 14
We might want to call the tlb check function without actually caring about
the real address resolution. Check if we really should write the value
back.
Signed-off-by: Alexander Graf
---
target-ppc/helper.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/target-ppc/he
Due to popular demand, this qdevifies the PCI host controller of 4xx SoCs
the same way as e500.
We have to introduce a small stub function for pci init that will be
removed in a later patch, once we qdev'ified the board, to keep the build
working.
Signed-off-by: Alexander Graf
---
hw/ppc440_bam
From: Benjamin Herrenschmidt
On the pseries machine (which expexts a paravirtualized guest), guest
access to PCI config space is via host-provided RTAS functions. This
patch extends these RTAS functions to permit access to PCI extended
config space, as specified in PAPR.
Signed-off-by: Benjamin
When using MAV 2.0 TLB registers, we have another range of TLB registers
available to read the supported page sizes from.
Add SPR definitions for those and add a helper function that we can use
to receive such a bitmap even when using MAV 1.0.
Signed-off-by: Alexander Graf
---
target-ppc/cpu.h
From: Benjamin Herrenschmidt
The kvm_get_dirty_pages_log_range() function uses two address
variables to step through the monitored memory region to update the
dirty log. However, these variables have type unsigned long, which
can overflow if running a 64-bit guest with a 32-bit qemu binary.
Thi
From: David Gibson
The pseries machine expects a para-virtualized guest and so supplies RTAS
functions (via a hypercall) for performing PCI config space access.
Currently the implementation of these calls into
pci_default_{read,write}_config(). However this would be incorrect for
any PCI device
E500mc supports IVORs 36-41. Add them to the support mask. Drop SPE
support too.
Signed-off-by: Alexander Graf
---
v1 -> v2:
- drop SPE IVOR
---
target-ppc/translate_init.c |6 +-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/target-ppc/translate_init.c b/target-ppc
Recent dtc doesn't compile our dts anymore. Change all hex numbers to have
0x prefixes, indicate the old version and recompile using recent dtc.
This doesn't change any semantics in the device tree.
Signed-off-by: Alexander Graf
---
pc-bios/bamboo.dtb | Bin 3179 -> 3211 bytes
pc-bios/bamboo.d
Today we're exposing a Virtex 440 CPU to the guest despite the fact
that we're telling the guest that we're running on a 440EP one in the
device tree.
So let's better default to a real 440EP to make things synced again.
Signed-off-by: Alexander Graf
---
hw/ppc440.c |2 +-
1 files changed, 1
Tabs followed by spaces are a no-go. My editor shows it red, distracting
me from actual work! :)
Signed-off-by: Alexander Graf
---
hw/ppc440_bamboo.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ppc440_bamboo.c b/hw/ppc440_bamboo.c
index 84e45b4..2369fba 10064
Thanks to Scott we now have an e500mc CPU description that works great with
KVM, but I have a personal dislike against targets that don't work emulated,
since their test coverage will be very low.
So this patch set implements TCG emulation for -cpu e500mc. I tested that it
works as expected agains
The PowerPC 2.06 BookE ISA defines an opcode called "tlbilx" which is used
to flush TLB entries. It's the recommended way of flushing in virtualized
environments.
So far we got away without implementing it, but Linux for e500mc uses this
instruction, so we better add it :).
Signed-off-by: Alexand
Back in the day when the bamboo target got introduced, the initial TLB was
dictated by KVM. TCG has been missing initial TLB values ever since, rendering
the target unusable for TCG usage.
This patch adds linear TLB maps the way Linux expects them, making the target
work.
Signed-off-by: Alexander
When accessing the device specific virtio config space, we memcpy
the data into a variable in QEMU. At that point we're basically
pulling host endianness into the game which is a really bad idea.
So instead, let's use the target specific load/store helpers for
memory pointers which fetch things in
From: David Gibson
This patch adds several auto-generated files to .gitignore which were
previously missing.
Signed-off-by: David Gibson
Signed-off-by: Alexander Graf
---
.gitignore |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/.gitignore b/.gitignore
index 406f7
From: Benjamin Herrenschmidt
load_image_targphys() gets passed a max size for the file, but doesn't
enforce it at all. Add a check and return -1 (error) if the file is
too big, without loading it. Fix the bracing style in the function
while we're at it.
Signed-off-by: Benjamin Herrenschmidt
Si
Now that we have the SoC init function in the same file, let's integrate
it with the board initialization.
While at it, also make use of the newly qdev'ified PCI host controller.
Signed-off-by: Alexander Graf
---
hw/ppc440_bamboo.c | 143 ++--
1
To be able to support CPU reset, we need to put all register initialization
and initial state into a CPU reset hook instead of a function that is only
called once on bootup.
This is a preparation step for the initial TLB setting code and brings bamboo
more in line with what e500 and virtex already
From: David Gibson
Back when I made patches introducing dma_addr_t and various PCI DMA
wrapper functions, I made a mistake. The bmdma_addr_{read,write} functions
need to take target_phys_addr_t not dma_addr_t, since they are assigned
to MemoryRegionOps callbacks.
This patch corrects my error.
From: Andreas Färber
Just like prep_pci.c, these were not associated with any MAINTAINERS
section, including PCI.
Signed-off-by: Andreas Färber
Cc: Alexander Graf
Signed-off-by: Alexander Graf
---
MAINTAINERS |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/MAINTAINE
From: Andreas Färber
Rename SysBus device from 'grackle' to 'grackle-pcihost' to resolve a
name conflict.
Also mark both devices as no_user.
Signed-off-by: Andreas Färber
Cc: Alexander Graf
Cc: Anthony Liguori
Signed-off-by: Alexander Graf
---
hw/grackle_pci.c | 17 -
1 f
Now that we have 440 TLB emulation, we can also support running the 440EP
CPU target in system emulation mode.
Signed-off-by: Alexander Graf
---
target-ppc/translate_init.c | 16 +---
1 files changed, 5 insertions(+), 11 deletions(-)
diff --git a/target-ppc/translate_init.c b/targ
We call pci_host_config_{read,write}_common() which perform PCI config
accesses. However they don't do all limit checking the way we expect
it to.
So let's introduce a small wrapper around them, making them behave the
way we would without touching generic code.
This patch is based on a patch by D
Hi Anthony / Aurelien / Blue,
This is my current patch queue for ppc. Please pull.
Alex
The following changes since commit 515689235c4c3d9c3f0406ddcdd21ed8da77062b:
Anthony Liguori (1):
Merge remote-tracking branch 'spice/spice.v47' into staging
are available in the git repository at
When using TCG with a BookE PowerPC core, we need to explicitly initialize
the BookE timers with the correct frequencies.
This was missing for 440EP, since that code came from KVM and was never used
with TCG.
Signed-off-by: Alexander Graf
---
hw/ppc440.c |1 +
1 files changed, 1 insertions(
When running a 440 target, we currently get invalid irq_num values (-1)
which completely confuse the IRQ setting code.
This is most likely due to the missing qdev conversion.
While this shouldn't happen in the first place and should really rather
be fixed by converting the target, I dislike segfa
From: Andreas Färber
Signed-off-by: Andreas Färber
Cc: Alexander Graf
Signed-off-by: Alexander Graf
---
MAINTAINERS |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index de2a916..a3bdb41 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -93,6
When setting a TLB entry, we need to check if the TLB we're putting it in
actually supports the given size. According to the 2.06 PowerPC ISA, a
value that's out of range can either be redefined to something implementation
dependent or we can raise an illegal opcode exception. We do the latter.
Si
Am 21.01.2012 05:19, schrieb Alexander Graf:
> From: Andreas Färber
>
> Signed-off-by: Andreas Färber
> Cc: Alexander Graf
> Signed-off-by: Alexander Graf
Patches 22, 23 and 26 have a "duplicate" Cc: line. You may want to fix
on your branch.
Andreas
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On 01/21/2012 02:08 AM, Michael Roth wrote:
The __attribute__((constructor)) init_main_loop() automatically get
called if qemu-tool.o is linked in. On win32, this leads to
a qemu_notify_event() call which attempts to SetEvent() on a HANDLE that
won't be initialized until qemu_init_main_loop() is
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