a bunch!
Regards
From: Peter Maydell
Sent: October 6, 2022 10:50 AM
To: a b
Cc: qemu-devel@nongnu.org
Subject: Re: A few QEMU questiosn
On Thu, 6 Oct 2022 at 08:34, a b wrote:
>
> Thanks a lot Peter for the clarification. It is very helpful.
>
&g
On Thu, 6 Oct 2022 at 08:34, a b wrote:
>
> Thanks a lot Peter for the clarification. It is very helpful.
>
> My naive understanding is that each MMU has only 1 TLB, why do we need an
> array of CPUTLBDescFast structures? How are these different CPUTLBDescFast
> data structures correlate with a
_
From: Peter Maydell
Sent: October 4, 2022 9:20 AM
To: a b
Cc: qemu-devel@nongnu.org
Subject: Re: A few QEMU questiosn
On Tue, 4 Oct 2022 at 02:10, a b wrote:
> I have a few newbie QEMU questions. I found that mmu_idx in aarch64-softmmu
> falls in 8, 10 and 12.
>
> I need
On Tue, 4 Oct 2022 at 02:10, a b wrote:
> I have a few newbie QEMU questions. I found that mmu_idx in aarch64-softmmu
> falls in 8, 10 and 12.
>
> I need some help to understand what they are for.
>
> I cannot find which macros are for mmu-idx 8, 10 and 12 at target/arm/cpu.h.
> It looks like
