On Tue, 4 Oct 2022 at 02:10, a b <blue_3...@hotmail.com> wrote: > I have a few newbie QEMU questions. I found that mmu_idx in aarch64-softmmu > falls in 8, 10 and 12. > > I need some help to understand what they are for. > > I cannot find which macros are for mmu-idx 8, 10 and 12 at target/arm/cpu.h. > It looks like all the values from ARMMMUIdx are greater than 0x10 > (ARM_MMU_IDX_A). Am I looking at the wrong place or missing something for the > different MMU modes in aarch64?
The comment in target/arm/cpu.h and the various enum definitions should be what you need. Note in particular the part that says "The ARMMMUIdx and the mmu index value used by the core QEMU TLB code are not quite the same" and also the functions in internals.h arm_to_core_mmu_idx() and core_to_arm_mmu_idx() which convert between these two representations. PS: there is a refactoring patch set currently in review which changes the MMU index allocation (essentially it collapses the separate Secure and NonSecure MMUIdx values together), so the specific details will likely change at some point this release cycle. thanks -- PMM
