On 2/21/24 10:41, Richard Henderson wrote:
Ho hum.. I just noticed that TALLINT only traps immediate write of 1, not also immediate
write of 0. So one helper for both MSR Xt and MSR imm is not practical.
Quick follow up to say that means you can do
static bool trans_MSR_i_ALLINT(DisasContext
On 2024/2/22 4:41, Richard Henderson wrote:
> On 2/21/24 09:09, Richard Henderson wrote:
>> On 2/21/24 03:08, Jinjie Ruan via wrote:
>>> Add ALLINT MSR (immediate) to decodetree. And the EL0 check is necessary
>>> to ALLINT. Avoid the unconditional write to pc and use
>>> raise_exception_ra
>>>
On 2024/2/22 3:09, Richard Henderson wrote:
> On 2/21/24 03:08, Jinjie Ruan via wrote:
>> Add ALLINT MSR (immediate) to decodetree. And the EL0 check is necessary
>> to ALLINT. Avoid the unconditional write to pc and use raise_exception_ra
>> to unwind.
>>
>> Signed-off-by: Jinjie Ruan
>> ---
>
On 2/21/24 09:09, Richard Henderson wrote:
On 2/21/24 03:08, Jinjie Ruan via wrote:
Add ALLINT MSR (immediate) to decodetree. And the EL0 check is necessary
to ALLINT. Avoid the unconditional write to pc and use raise_exception_ra
to unwind.
Signed-off-by: Jinjie Ruan
---
target/arm/tcg/a64.
On 2/21/24 09:09, Richard Henderson wrote:
+static bool trans_MSR_i_ALLINT(DisasContext *s, arg_i *a)
+{
+ if (!dc_isar_feature(aa64_nmi, s) || s->current_el == 0) {
+ return false;
+ }
+ gen_helper_msr_i_allint(tcg_env, tcg_constant_i32(a->imm));
You're passing all of #imm4, no
On 2/21/24 03:08, Jinjie Ruan via wrote:
Add ALLINT MSR (immediate) to decodetree. And the EL0 check is necessary
to ALLINT. Avoid the unconditional write to pc and use raise_exception_ra
to unwind.
Signed-off-by: Jinjie Ruan
---
target/arm/tcg/a64.decode | 1 +
target/arm/tcg/helper-a
