On 2/21/24 10:41, Richard Henderson wrote:
Ho hum.. I just noticed that TALLINT only traps immediate write of 1, not also immediate
write of 0. So one helper for both MSR Xt and MSR imm is not practical.
Quick follow up to say that means you can do
static bool trans_MSR_i_ALLINT(DisasContext *s, arg_i *a)
{
if (!dc_isar_feature(aa64_nmi, s)
|| s->current_el == 0
|| (a->imm & ~1)) {
return false;
}
if (!a->imm) {
clear_pstate_bits(PSTATE_ALLINT);
} else if (arm_dc_feature(s, ARM_FEATURE_EL2) && s->current_el == 1) {
/* Use helper for runtime check against HCRX_EL2.TALLINT. */
gen_helper_msr_set_allint_el1(tcg_env);
} else {
set_pstate_bits(PSTATE_ALLINT);
}
return true;
}
Generate inline bit ops whenever TALLINT does not apply.
This also means the helper need not check current_el, because we've already
done it here.
r~
