Thanks Peter for your response. I notice that *tlb_fill()* is happening
only in *softmmu_template.h *and not anywhere else in code base. This means
I should expect the TLB itself to be populated here for other code loads to
have successful look up later. Am I wrong with my understanding?
Even I g
On 6 June 2015 at 08:36, Sandhya Kumar wrote:
> Thanks Peter for your explanation.
>
> [The following question on TLB working could be a deviation from the first
> mail here, but asking here instead of starting new thread.]
>
> I picked up a simple 'Hello world' ELF executable (shown at the end) a
Thanks Peter for your explanation.
[The following question on TLB working could be a deviation from the first
mail here, but asking here instead of starting new thread.]
I picked up a simple 'Hello world' ELF executable (shown at the end) and
tried to experiment with QEMU's address translations (
On 3 June 2015 at 10:24, Sandhya Kumar wrote:
> Well, I think we can also achieve this like adding a flag in the structure
> of CPUTLBEntry.
> Am I missing something?
The point of the TLB data structure is to allow very fast access
in the common case of "TLB hit to guest RAM". If we had extra
fla
Well, I think we can also achieve this like adding a flag in the structure
of CPUTLBEntry.
Am I missing something?
On Wed, Jun 3, 2015 at 4:22 PM, Paolo Bonzini wrote:
>
>
> On 03/06/2015 10:07, Sandhya Kumar wrote:
> > Thanks again. One more question.
> >
> > On versions prior to the mentioned
On 03/06/2015 10:07, Sandhya Kumar wrote:
> Thanks again. One more question.
>
> On versions prior to the mentioned commit, is there any specific reason
> (in x86 source code of QEMU) to choose separate modes for address
> translations (of kernel and user mode)? Or was that done just for
> perfo
Thanks again. One more question.
On versions prior to the mentioned commit, is there any specific reason (in
x86 source code of QEMU) to choose separate modes for address translations
(of kernel and user mode)? Or was that done just for performance
improvement?
On Wed, Jun 3, 2015 at 3:58 PM, P
On 03/06/2015 09:41, Sandhya Kumar wrote:
> Thanks for your mail. Are these TLB modes logic specific to QEMU
> implementation for x86?
Yes, they are specific to QEMU.
> Asking this as I am not able to get any information about seperate TLBs
> from Intel developer manuals
Real hardware TLBs p
Thanks for your mail. Are these TLB modes logic specific to QEMU
implementation for x86?
Asking this as I am not able to get any information about seperate TLBs
from Intel developer manuals
On Wed, Jun 3, 2015 at 3:01 PM, Paolo Bonzini wrote:
>
>
> On 03/06/2015 08:51, Sandhya Kumar wrote:
> >
On 03/06/2015 08:51, Sandhya Kumar wrote:
> As per my understanding (which matches versions prior to this commit),
> we generally maintain only two TLBs [one for kernel and one for user] in
> x86 ISA for caching address translations. With this commit we seem to
> have three modes of MMU, although
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