Thanks for your mail. Are these TLB modes logic specific to QEMU implementation for x86? Asking this as I am not able to get any information about seperate TLBs from Intel developer manuals
On Wed, Jun 3, 2015 at 3:01 PM, Paolo Bonzini <pbonz...@redhat.com> wrote: > > > On 03/06/2015 08:51, Sandhya Kumar wrote: > > As per my understanding (which matches versions prior to this commit), > > we generally maintain only two TLBs [one for kernel and one for user] in > > x86 ISA for caching address translations. With this commit we seem to > > have three modes of MMU, although only two will be actually used (either > > KSMAP or KNOSMAP). > > This is not accurate. If AC=0, data accesses from the kernel use > KNOSMAP, but implicit accesses (e.g. reads of the IDT) use KSMAP. > > > Is my claim valid ? Why cannot those two original > > modes serve the purpose and why is the separation (of KNOMAP and KSMAP) > > needed? > > Because the QEMU TLB just has a single bit for "is this page readable". > In supervisor mode and with SMAP enabled, this changes depending on the > value of the AC bit. Without separate TLBs for KNOSMAP/KSMAP, you would > have to flush the TLB on every CLAC or STAC instruction. > > Paolo >
