Re: [Qemu-devel] [PATCH v5 3/9] target-ppc: Implement mtvsrws instruction

2016-09-28 Thread Richard Henderson
On 09/28/2016 07:19 PM, Nikunj A Dadhania wrote: Richard Henderson writes: On 09/28/2016 11:41 AM, Nikunj A Dadhania wrote: +tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]); +tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), t0, t0, 32, 32); Why are you using t0? Thought about dropping

Re: [Qemu-devel] [PATCH v5 3/9] target-ppc: Implement mtvsrws instruction

2016-09-28 Thread Richard Henderson
On 09/28/2016 06:53 PM, David Gibson wrote: On Wed, Sep 28, 2016 at 01:21:00PM -0700, Richard Henderson wrote: On 09/28/2016 11:41 AM, Nikunj A Dadhania wrote: +tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]); +tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), t0, t0, 32, 32); Why are you

Re: [Qemu-devel] [PATCH v5 3/9] target-ppc: Implement mtvsrws instruction

2016-09-28 Thread David Gibson
On Wed, Sep 28, 2016 at 01:21:00PM -0700, Richard Henderson wrote: > On 09/28/2016 11:41 AM, Nikunj A Dadhania wrote: > > +tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]); > > +tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), t0, t0, 32, 32); > > Why are you using t0? Richard, I don't quite u

Re: [Qemu-devel] [PATCH v5 3/9] target-ppc: Implement mtvsrws instruction

2016-09-28 Thread Nikunj A Dadhania
Richard Henderson writes: > On 09/28/2016 11:41 AM, Nikunj A Dadhania wrote: >> +tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]); >> +tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), t0, t0, 32, 32); > > Why are you using t0? Thought about dropping it, but wasn't sure if deposit_i64 would ch

Re: [Qemu-devel] [PATCH v5 3/9] target-ppc: Implement mtvsrws instruction

2016-09-28 Thread Richard Henderson
On 09/28/2016 11:41 AM, Nikunj A Dadhania wrote: > +tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]); > +tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), t0, t0, 32, 32); Why are you using t0? r~