On Wed, Sep 28, 2016 at 01:21:00PM -0700, Richard Henderson wrote: > On 09/28/2016 11:41 AM, Nikunj A Dadhania wrote: > > + tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]); > > + tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), t0, t0, 32, 32); > > Why are you using t0?
Richard, I don't quite understand your question. This looks correct
to me. It's duplicating the low 32-bits of rA into both the low-and
high 32-bits of t0, which will then be store to both the low and high
64-bit elements of the VSR. That matches the instruction definition
which puts the low 32-bits of RA into every 32-bit element of the
vector.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
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