On Tue, 26 Mar 2019 00:50:53 +0900,
Richard Henderson wrote:
>
> On 3/25/19 2:38 AM, Yoshinori Sato wrote:
> >>> +static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a)
> >>> +{
> >>> +TCGv val, mem;
> >>> +mem = tcg_temp_new();
> >>> +val = rx_load_source(ctx, mem, a->ld, a->mi,
On Tue, 26 Mar 2019 00:50:53 +0900,
Richard Henderson wrote:
>
> On 3/25/19 2:38 AM, Yoshinori Sato wrote:
> >>> +static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a)
> >>> +{
> >>> +TCGv val, mem;
> >>> +mem = tcg_temp_new();
> >>> +val = rx_load_source(ctx, mem, a->ld, a->mi,
On 3/25/19 2:38 AM, Yoshinori Sato wrote:
>>> +static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a)
>>> +{
>>> +TCGv val, mem;
>>> +mem = tcg_temp_new();
>>> +val = rx_load_source(ctx, mem, a->ld, a->mi, a->rs);
>>> +tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[a->rd + 1],
>>
On Thu, 21 Mar 2019 14:40:11 +0900,
Richard Henderson wrote:
>
> On 3/20/19 7:15 AM, Yoshinori Sato wrote:
> > +/* [ri, rb] */
> > +static inline void rx_gen_regindex(DisasContext *ctx, TCGv mem,
>
> Please drop all of the inline markers.
> Let the compiler choose which are profitable to inline.
On 3/20/19 7:15 AM, Yoshinori Sato wrote:
> +/* [ri, rb] */
> +static inline void rx_gen_regindex(DisasContext *ctx, TCGv mem,
Please drop all of the inline markers.
Let the compiler choose which are profitable to inline.
> +/* load source operand */
> +static inline TCGv rx_load_source(DisasCon
On 3/20/19 5:09 PM, Aleksandar Markovic wrote:
> This patch is really large.How about splitting it into a dozen of smaller
> logical groups? Also, a successful build (both gcc and clang kinds) is
> required after each patch.
Successful builds are often not feasible for new ports, since most ofte
On Wednesday, March 20, 2019, Yoshinori Sato
wrote:
> This part only supported RXv1 instructions.
> Instruction manual.
> https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_
> family/r01us0032ej0120_rxsm.pdf
>
> Signed-off-by: Yoshinori Sato
> ---
Hello,, Yoshinori.
This patch is really
