On Wed, Sep 25, 2013 at 08:36:09AM +0900, Peter Maydell wrote:
> On 25 September 2013 00:41, Michael S. Tsirkin wrote:
> > On Tue, Sep 24, 2013 at 08:21:50PM +0900, Peter Maydell wrote:
> > Right. You might be able to use MR hierarchy to find the last bridge to
> > claim transaction. That should
On 25 September 2013 00:41, Michael S. Tsirkin wrote:
> On Tue, Sep 24, 2013 at 08:21:50PM +0900, Peter Maydell wrote:
> Right. You might be able to use MR hierarchy to find the last bridge to
> claim transaction. That should to be enough for PCI, for express you
> then need to find all devices o
On Tue, Sep 24, 2013 at 06:41:11PM +0300, Michael S. Tsirkin wrote:
> On Tue, Sep 24, 2013 at 08:21:50PM +0900, Peter Maydell wrote:
> > On 24 September 2013 20:17, Marcel Apfelbaum wrote:
> > > I was suggesting an algorithm to find the MA device in order
> > > to set MA Received Bit in its Status
On Tue, Sep 24, 2013 at 08:21:50PM +0900, Peter Maydell wrote:
> On 24 September 2013 20:17, Marcel Apfelbaum wrote:
> > I was suggesting an algorithm to find the MA device in order
> > to set MA Received Bit in its Status(Sec_Status) register.
> >
> > The algorithm was to traverse the PCI buses f
On Tue, 2013-09-24 at 20:21 +0900, Peter Maydell wrote:
> On 24 September 2013 20:17, Marcel Apfelbaum wrote:
> > I was suggesting an algorithm to find the MA device in order
> > to set MA Received Bit in its Status(Sec_Status) register.
> >
> > The algorithm was to traverse the PCI buses for find
On 24 September 2013 20:17, Marcel Apfelbaum wrote:
> I was suggesting an algorithm to find the MA device in order
> to set MA Received Bit in its Status(Sec_Status) register.
>
> The algorithm was to traverse the PCI buses for finding the
> MA device using the transaction address.
Yes. My point
On Tue, 2013-09-24 at 19:55 +0900, Peter Maydell wrote:
> On 24 September 2013 19:44, Marcel Apfelbaum wrote:
> > We need to check all the bridges on each bus encountered
> > for their address range; if it corresponds to the transaction address,
> > we pass the bridge to the other bus(depending on
On 24 September 2013 19:44, Marcel Apfelbaum wrote:
> We need to check all the bridges on each bus encountered
> for their address range; if it corresponds to the transaction address,
> we pass the bridge to the other bus(depending on transaction's direction).
I haven't looked at all at the detai
On Tue, 2013-09-24 at 11:58 +0300, Michael S. Tsirkin wrote:
> corrected Anthony's mail.
>
> On Tue, Sep 24, 2013 at 11:44:57AM +0300, Marcel Apfelbaum wrote:
> > > Not necessarily. Another bridge can claim it then
> > > terminate with MA.
> > >
> > > Example:
> > >
> > > -[:00]-+-00.0
> > >
On Tue, Sep 24, 2013 at 11:07:19AM +0300, Marcel Apfelbaum wrote:
> On Mon, 2013-09-23 at 21:45 +0300, Michael S. Tsirkin wrote:
> > On Mon, Sep 23, 2013 at 08:49:53PM +0300, Marcel Apfelbaum wrote:
> > > On Mon, 2013-09-23 at 18:10 +0300, Michael S. Tsirkin wrote:
> > > > On Mon, Sep 23, 2013 at 0
corrected Anthony's mail.
On Tue, Sep 24, 2013 at 11:44:57AM +0300, Marcel Apfelbaum wrote:
> > Not necessarily. Another bridge can claim it then
> > terminate with MA.
> >
> > Example:
> >
> > -[:00]-+-00.0
> >+-02.0
> >+-16.0
> >+-16.3
> >+-1
On Tue, 2013-09-24 at 11:29 +0300, Michael S. Tsirkin wrote:
> On Tue, Sep 24, 2013 at 11:07:19AM +0300, Marcel Apfelbaum wrote:
> > On Mon, 2013-09-23 at 21:45 +0300, Michael S. Tsirkin wrote:
> > > On Mon, Sep 23, 2013 at 08:49:53PM +0300, Marcel Apfelbaum wrote:
> > > > On Mon, 2013-09-23 at 18:
On Mon, 2013-09-23 at 21:45 +0300, Michael S. Tsirkin wrote:
> On Mon, Sep 23, 2013 at 08:49:53PM +0300, Marcel Apfelbaum wrote:
> > On Mon, 2013-09-23 at 18:10 +0300, Michael S. Tsirkin wrote:
> > > On Mon, Sep 23, 2013 at 05:43:38PM +0300, Marcel Apfelbaum wrote:
> > > > On Mon, 2013-09-23 at 16:
On Mon, Sep 23, 2013 at 08:49:53PM +0300, Marcel Apfelbaum wrote:
> On Mon, 2013-09-23 at 18:10 +0300, Michael S. Tsirkin wrote:
> > On Mon, Sep 23, 2013 at 05:43:38PM +0300, Marcel Apfelbaum wrote:
> > > On Mon, 2013-09-23 at 16:45 +0300, Michael S. Tsirkin wrote:
> > > > On Mon, Sep 23, 2013 at 0
On Mon, 2013-09-23 at 18:10 +0300, Michael S. Tsirkin wrote:
> On Mon, Sep 23, 2013 at 05:43:38PM +0300, Marcel Apfelbaum wrote:
> > On Mon, 2013-09-23 at 16:45 +0300, Michael S. Tsirkin wrote:
> > > On Mon, Sep 23, 2013 at 03:37:43PM +0300, Marcel Apfelbaum wrote:
> > > > On Mon, 2013-09-23 at 14:
On Mon, 2013-09-23 at 16:45 +0300, Michael S. Tsirkin wrote:
> On Mon, Sep 23, 2013 at 03:37:43PM +0300, Marcel Apfelbaum wrote:
> > On Mon, 2013-09-23 at 14:27 +0300, Michael S. Tsirkin wrote:
> > > On Mon, Sep 23, 2013 at 02:01:17PM +0300, Marcel Apfelbaum wrote:
> > > > This patch is implemented
On Mon, Sep 23, 2013 at 05:43:38PM +0300, Marcel Apfelbaum wrote:
> On Mon, 2013-09-23 at 16:45 +0300, Michael S. Tsirkin wrote:
> > On Mon, Sep 23, 2013 at 03:37:43PM +0300, Marcel Apfelbaum wrote:
> > > On Mon, 2013-09-23 at 14:27 +0300, Michael S. Tsirkin wrote:
> > > > On Mon, Sep 23, 2013 at 0
On Mon, Sep 23, 2013 at 03:37:43PM +0300, Marcel Apfelbaum wrote:
> On Mon, 2013-09-23 at 14:27 +0300, Michael S. Tsirkin wrote:
> > On Mon, Sep 23, 2013 at 02:01:17PM +0300, Marcel Apfelbaum wrote:
> > > This patch is implemented on top of series:
> > > [PATCH v5 0/3] pci: implement upstream maste
On Mon, 2013-09-23 at 14:27 +0300, Michael S. Tsirkin wrote:
> On Mon, Sep 23, 2013 at 02:01:17PM +0300, Marcel Apfelbaum wrote:
> > This patch is implemented on top of series:
> > [PATCH v5 0/3] pci: implement upstream master abort protocol
> >
> > Added "master abort io" background region for PC
On Mon, Sep 23, 2013 at 02:01:17PM +0300, Marcel Apfelbaum wrote:
> This patch is implemented on top of series:
> [PATCH v5 0/3] pci: implement upstream master abort protocol
>
> Added "master abort io" background region for PCIBus.
>
> Added "master abort mem" region to catch transactions initia
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