On Fri, 28 Feb 2025 at 00:18, Richard Henderson
wrote:
>
> On 2/27/25 09:58, Peter Maydell wrote:
> > On Thu, 27 Feb 2025 at 17:41, Richard Henderson
> > wrote:
> >>
> >> On 2/27/25 06:27, Peter Maydell wrote:
> >>> +static void do_ldrd_load(DisasContext *s, TCGv_i32 addr, int rt, int rt2)
> >>>
On 2/27/25 09:58, Peter Maydell wrote:
On Thu, 27 Feb 2025 at 17:41, Richard Henderson
wrote:
On 2/27/25 06:27, Peter Maydell wrote:
+static void do_ldrd_load(DisasContext *s, TCGv_i32 addr, int rt, int rt2)
+{
+/*
+ * LDRD is required to be an atomic 64-bit access if the
+ * addr
On 2/27/25 06:27, Peter Maydell wrote:
Our LDRD implementation is wrong in two respects:
* if the address is 4-aligned and the load crosses a page boundary
and the second load faults and the first load was to the
base register (as in cases like "ldrd r2, r3, [r2]", then we
must not
On Thu, 27 Feb 2025 at 17:41, Richard Henderson
wrote:
>
> On 2/27/25 06:27, Peter Maydell wrote:
> > +static void do_ldrd_load(DisasContext *s, TCGv_i32 addr, int rt, int rt2)
> > +{
> > +/*
> > + * LDRD is required to be an atomic 64-bit access if the
> > + * address is 8-aligned, tw
