On 8/17/20 1:48 AM, frank.ch...@sifive.com wrote:
> From: Frank Chang
>
> Introduce the concepts of fractional LMUL for RVV 1.0.
> In RVV 1.0, LMUL bits are contiguous in vtype register.
>
> Signed-off-by: Frank Chang
> ---
> target/riscv/cpu.h | 15 ---
> target/riscv/tr
From: Frank Chang
Introduce the concepts of fractional LMUL for RVV 1.0.
In RVV 1.0, LMUL bits are contiguous in vtype register.
Signed-off-by: Frank Chang
---
target/riscv/cpu.h | 15 ---
target/riscv/translate.c | 16 ++--
target/riscv/vector_helper.c |
