Re: [RFC v2 13/76] target/riscv: rvv-0.9: add vlenb register

On 7/22/20 2:15 AM, frank.ch...@sifive.com wrote: > From: Greentime Hu > > Signed-off-by: Greentime Hu > Signed-off-by: Frank Chang > --- > target/riscv/cpu_bits.h | 1 + > target/riscv/csr.c | 7 +++ > 2 files changed, 8 insertions(+) Reviewed-by: Richard Henderson r~

[RFC v2 13/76] target/riscv: rvv-0.9: add vlenb register

From: Greentime Hu Signed-off-by: Greentime Hu Signed-off-by: Frank Chang --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 7 +++ 2 files changed, 8 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7afdd4814b..fe055b67a6 100644 --- a/target/ri