Re: [RFC v2 13/76] target/riscv: rvv-0.9: add vlenb register

[Richard Henderson]

On 7/22/20 2:15 AM, frank.ch...@sifive.com wrote:
> From: Greentime Hu <greentime...@sifive.com>
> 
> Signed-off-by: Greentime Hu <greentime...@sifive.com>
> Signed-off-by: Frank Chang <frank.ch...@sifive.com>
> ---
>  target/riscv/cpu_bits.h | 1 +
>  target/riscv/csr.c      | 7 +++++++
>  2 files changed, 8 insertions(+)

Reviewed-by: Richard Henderson <richard.hender...@linaro.org>


r~