On 11/18/07, Robert Reif <[EMAIL PROTECTED]> wrote:
> Blue Swirl wrote:
>
> >On 11/16/07, Robert Reif <[EMAIL PROTECTED]> wrote:
> >
> >
> >>>This patch fixes the word order for 64 bit reads of the mxcc registers.
> >>>
> >>>
> >
> >Otherwise everything seems OK, but it breaks NetBSD version 3 on S
Blue Swirl wrote:
On 11/18/07, Robert Reif <[EMAIL PROTECTED]> wrote:
Blue Swirl wrote:
On 11/16/07, Robert Reif <[EMAIL PROTECTED]> wrote:
This patch fixes the word order for 64 bit reads of the mxcc registers.
Otherwise everything seems OK, but it breaks NetB
On 11/18/07, Robert Reif <[EMAIL PROTECTED]> wrote:
> Blue Swirl wrote:
>
> >On 11/16/07, Robert Reif <[EMAIL PROTECTED]> wrote:
> >
> >
> >>>This patch fixes the word order for 64 bit reads of the mxcc registers.
> >>>
> >>>
> >
> >Otherwise everything seems OK, but it breaks NetBSD version 3 on S
Blue Swirl wrote:
On 11/16/07, Robert Reif <[EMAIL PROTECTED]> wrote:
This patch fixes the word order for 64 bit reads of the mxcc registers.
Otherwise everything seems OK, but it breaks NetBSD version 3 on SS10:
clock0 at obio0 slot 0 offset 0x20: mk48t08
timer0 at obio0 slot 0
On 11/16/07, Robert Reif <[EMAIL PROTECTED]> wrote:
> >
> >
> >This patch fixes the word order for 64 bit reads of the mxcc registers.
Otherwise everything seems OK, but it breaks NetBSD version 3 on SS10:
clock0 at obio0 slot 0 offset 0x20: mk48t08
timer0 at obio0 slot 0 offset 0x30data f
This patch fixes the word order for 64 bit reads of the mxcc registers.
Index: target-sparc/op_helper.c
===
RCS file: /sources/qemu/qemu/target-sparc/op_helper.c,v
retrieving revision 1.52
diff -p -u -r1.52 op_helper.c
--- targ
On 11/15/07, Robert Reif <[EMAIL PROTECTED]> wrote:
> This patch fixes the word order for 64 bit reads of the mxcc registers.
>
> It returns the high 32 bits in ret and the lower 32 bits in T0 just
> like other places in the same function.
>
> T0 is defined as: register uint32_t T0 asm(AREG1);
>
>
This patch fixes the word order for 64 bit reads of the mxcc registers.
It returns the high 32 bits in ret and the lower 32 bits in T0 just
like other places in the same function.
T0 is defined as: register uint32_t T0 asm(AREG1);
T0 on my machine has a sizeof = 4. Because of this, I don't thi
