On 08/03/2017 03:13 PM, Thomas Huth wrote:
On 03.08.2017 14:08, KONRAD Frederic wrote:
On 08/03/2017 01:37 PM, Thomas Huth wrote:
On 01.08.2017 10:44, KONRAD Frederic wrote:
When a tlb instruction miss happen, rw is set to 0 at the bottom
of cpu_ppc_handle_mmu_fault which cause the MAS upd
On 03.08.2017 14:08, KONRAD Frederic wrote:
>
>
> On 08/03/2017 01:37 PM, Thomas Huth wrote:
>> On 01.08.2017 10:44, KONRAD Frederic wrote:
>>> When a tlb instruction miss happen, rw is set to 0 at the bottom
>>> of cpu_ppc_handle_mmu_fault which cause the MAS update function to miss
>>> the SAS
On 08/03/2017 01:37 PM, Thomas Huth wrote:
On 01.08.2017 10:44, KONRAD Frederic wrote:
When a tlb instruction miss happen, rw is set to 0 at the bottom
of cpu_ppc_handle_mmu_fault which cause the MAS update function to miss
the SAS and TS bit in MAS6, MAS1 in booke206_update_mas_tlb_miss.
Jus
On 01.08.2017 10:44, KONRAD Frederic wrote:
> When a tlb instruction miss happen, rw is set to 0 at the bottom
> of cpu_ppc_handle_mmu_fault which cause the MAS update function to miss
> the SAS and TS bit in MAS6, MAS1 in booke206_update_mas_tlb_miss.
>
> Just calling booke206_update_mas_tlb_miss
