On 01.08.2017 10:44, KONRAD Frederic wrote: > When a tlb instruction miss happen, rw is set to 0 at the bottom > of cpu_ppc_handle_mmu_fault which cause the MAS update function to miss > the SAS and TS bit in MAS6, MAS1 in booke206_update_mas_tlb_miss. > > Just calling booke206_update_mas_tlb_miss with rw = 2 solve the issue. > > Signed-off-by: KONRAD Frederic <frederic.kon...@adacore.com> > --- > target/ppc/mmu_helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c > index b7b9088..f06b938 100644 > --- a/target/ppc/mmu_helper.c > +++ b/target/ppc/mmu_helper.c > @@ -1551,7 +1551,7 @@ static int cpu_ppc_handle_mmu_fault(CPUPPCState *env, > target_ulong address, > env->spr[SPR_40x_ESR] = 0x00000000; > break; > case POWERPC_MMU_BOOKE206: > - booke206_update_mas_tlb_miss(env, address, rw); > + booke206_update_mas_tlb_miss(env, address, 2);
Couldn't that code path be called for normal data read miss (instead of instruction miss), too? Anyway, could we please use MMU_INST_FETCH instead of magic values like 2 here? Thomas
