On 14/06/2019 14:10, Palmer Dabbelt wrote:
> Sorry this took a while to fix, I've just sent a patch to fix the memory leak.
Thank you for taking care of this!
On Thu, 30 May 2019 03:57:12 PDT (-0700), Peter Maydell wrote:
On Sun, 26 May 2019 at 02:10, Palmer Dabbelt wrote:
From: Fabien Chouteau
QEMU model of the GPIO device on the SiFive E300 series SOCs.
The pins are not used by a board definition yet, however this
implementation can already be
On Sun, 26 May 2019 at 02:10, Palmer Dabbelt wrote:
>
> From: Fabien Chouteau
>
> QEMU model of the GPIO device on the SiFive E300 series SOCs.
>
> The pins are not used by a board definition yet, however this
> implementation can already be used to trigger GPIO interrupts from the
> software by
From: Fabien Chouteau
QEMU model of the GPIO device on the SiFive E300 series SOCs.
The pins are not used by a board definition yet, however this
implementation can already be used to trigger GPIO interrupts from the
software by configuring a pin as both output and input.
Signed-off-by: Fabien
