On Sun, 26 May 2019 at 02:10, Palmer Dabbelt <pal...@sifive.com> wrote:
>
> From: Fabien Chouteau <chout...@adacore.com>
>
> QEMU model of the GPIO device on the SiFive E300 series SOCs.
>
> The pins are not used by a board definition yet, however this
> implementation can already be used to trigger GPIO interrupts from the
> software by configuring a pin as both output and input.
>
> Signed-off-by: Fabien Chouteau <chout...@adacore.com>
> Reviewed-by: Palmer Dabbelt <pal...@sifive.com>
> Signed-off-by: Palmer Dabbelt <pal...@sifive.com>
Hi; this patch causes Coverity to complain about a memory
leak (CID 1401707):
> static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp)
> {
> const struct MemmapEntry *memmap = sifive_e_memmap;
> + Error *err = NULL;
>
> SiFiveESoCState *s = RISCV_E_SOC(dev);
> MemoryRegion *sys_mem = get_system_memory();
> @@ -184,8 +188,28 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev,
> Error **errp)
> sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon",
> memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
> sifive_prci_create(memmap[SIFIVE_E_PRCI].base);
> - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.gpio0",
> - memmap[SIFIVE_E_GPIO0].base, memmap[SIFIVE_E_GPIO0].size);
> +
> + /* GPIO */
> +
> + object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
This function allocated xip_mem and mask_rom via g_new() but
then this error-exit doesn't free them.
The best way to fix this is to stop doing separate memory
allocations at all -- instead just have fields in the
SiFiveESoCState struct
MemoryRegion xip_mem;
Memory_Region mask_rom;
and pass &s->xip_mem etc where currently the code uses xip_mem.
thanks
-- PMM
