On 03/05/2013 12:34 AM, Paul Brook wrote:
>>> Because we're actually storing two halves of a 128-bit value. You still
>>> store the least significant half first.
>>
>> Right, I'm sorry I didn't see you comment was only about the Q registers.
>> What would be the solution then?
>>
>> #ifdef TARGET
On 03/04/2013 02:30 PM, Paul Brook wrote:
"The bytes with the register are transmitted in target byte order."
/* Aliases for Q regs. */
nregs += 16;
if (reg < nregs) {
-stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
-
> >> "The bytes with the register are transmitted in target byte order."
> >>
> >> /* Aliases for Q regs. */
> >> nregs += 16;
> >> if (reg < nregs) {
> >>
> >> -stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
> >> -stfq_le_p(buf + 8, env->vfp.re
On 03/01/2013 09:51 PM, Paul Brook wrote:
>> From GDB Remote Serial Protocol doc:
>>
>> "The bytes with the register are transmitted in target byte order."
>
>> /* Aliases for Q regs. */
>> nregs += 16;
>> if (reg < nregs) {
>>
>> -stfq_le_p(buf, env->vfp.re
> From GDB Remote Serial Protocol doc:
>
> "The bytes with the register are transmitted in target byte order."
> /* Aliases for Q regs. */
> nregs += 16;
> if (reg < nregs) {
>
> -stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
> -stfq_le_p(buf
>From GDB Remote Serial Protocol doc:
"The bytes with the register are transmitted in target byte order."
Signed-off-by: Fabien Chouteau
---
target-arm/helper.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index e9
