On 16 July 2018 at 23:23, Guenter Roeck wrote:
> Writes in PIO mode have two requirements:
>
> - A data interrupt must be generated after a write command has been
> issued to indicate that the chip is ready to receive data.
> - A block interrupt must be generated after each block to indicate
>
On Mon, Jul 16, 2018 at 10:20:37PM -0300, Philippe Mathieu-Daudé wrote:
> Cc'ing ANTField folks who might have the specs.
>
> On 07/16/2018 07:23 PM, Guenter Roeck wrote:
> > Writes in PIO mode have two requirements:
> >
> > - A data interrupt must be generated after a write command has been
> >
Cc'ing ANTField folks who might have the specs.
On 07/16/2018 07:23 PM, Guenter Roeck wrote:
> Writes in PIO mode have two requirements:
>
> - A data interrupt must be generated after a write command has been
> issued to indicate that the chip is ready to receive data.
> - A block interrupt mus
Writes in PIO mode have two requirements:
- A data interrupt must be generated after a write command has been
issued to indicate that the chip is ready to receive data.
- A block interrupt must be generated after each block to indicate
that the chip is ready to receive the next data block.
Re
