Re: [PATCH v5 1/4] target/riscv: add vector extension field in CPURISCVState

2020-02-27 Thread Richard Henderson
On 2/21/20 1:45 AM, LIU Zhiwei wrote: > The 32 vector registers will be viewed as a continuous memory block. > It avoids the convension between element index and (regno, offset). > Thus elements can be directly accessed by offset from the first vector > base address. > > Signed-off-by: LIU Zhiwei

Re: [PATCH v5 1/4] target/riscv: add vector extension field in CPURISCVState

2020-02-26 Thread Alistair Francis
On Fri, Feb 21, 2020 at 1:45 AM LIU Zhiwei wrote: > > The 32 vector registers will be viewed as a continuous memory block. > It avoids the convension between element index and (regno, offset). > Thus elements can be directly accessed by offset from the first vector > base address. > > Signed-off-b

[PATCH v5 1/4] target/riscv: add vector extension field in CPURISCVState

2020-02-21 Thread LIU Zhiwei
The 32 vector registers will be viewed as a continuous memory block. It avoids the convension between element index and (regno, offset). Thus elements can be directly accessed by offset from the first vector base address. Signed-off-by: LIU Zhiwei --- target/riscv/cpu.h | 12 1 file