On 3/23/20 1:10 AM, LIU Zhiwei wrote:
>> static void gen_gvec_rsubi(unsigned vece, uint32_t dofs,
>> uint32_t aofs, int64_t c,
>> uint32_t oprsz, uint32_t maxsz)
>> {
>> tcg_debug_assert(vece <= MO_64);
>> tcg_gen_gvec_2i(dofs, aofs, oprsz, maxsz, c, &rsub_op[vece]);
>> }
> Hi Richa
On 2020/3/14 13:25, Richard Henderson wrote:
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
+if (a->vm && s->vl_eq_vlmax) { \
+tcg_gen_gvec_##GVSUF(8 << s->sew, vreg_ofs(s, a->rd), \
+vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1), \
+
On 2020/3/14 13:25, Richard Henderson wrote:
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
+if (a->vm && s->vl_eq_vlmax) { \
+tcg_gen_gvec_##GVSUF(8 << s->sew, vreg_ofs(s, a->rd), \
+vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1), \
On 3/12/20 7:58 AM, LIU Zhiwei wrote:
> +if (a->vm && s->vl_eq_vlmax) { \
> +tcg_gen_gvec_##GVSUF(8 << s->sew, vreg_ofs(s, a->rd), \
> +vreg_ofs(s, a->rs2), vreg_ofs(s, a->rs1), \
> +MAXSZ(s), MAXSZ(s));
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 21 +++
target/riscv/insn32.decode | 10 ++
target/riscv/insn_trans/trans_rvv.inc.c | 220
target/riscv/vector_helper.c| 122 +
4 files changed, 373 insertions(+
