On 2/17/23 10:29 AM, Jonathan Cameron wrote:
We are missing necessary config write handling for AER emulation in
the CXL root port. Add it based on pcie_root_port.c
Signed-off-by: Jonathan Cameron
Reviewed-by: Dave Jiang
---
hw/pci-bridge/cxl_root_port.c | 3 +++
1 file changed, 3 in
We are missing necessary config write handling for AER emulation in
the CXL root port. Add it based on pcie_root_port.c
Signed-off-by: Jonathan Cameron
---
hw/pci-bridge/cxl_root_port.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_
