Re: [PATCH v4 20/20] target/riscv: Enable uxl field write

2021-11-19 Thread Alistair Francis
On Fri, Nov 12, 2021 at 2:14 AM LIU Zhiwei wrote: > > Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu_bits.h | 2 ++ > target/riscv/csr.c | 8 +--- > 2 files changed, 7 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/cpu_bits.h b

Re: [PATCH v4 20/20] target/riscv: Enable uxl field write

2021-11-11 Thread Richard Henderson
On 11/11/21 4:51 PM, LIU Zhiwei wrote: Signed-off-by: LIU Zhiwei --- target/riscv/cpu_bits.h | 2 ++ target/riscv/csr.c | 8 +--- 2 files changed, 7 insertions(+), 3 deletions(-) Works for me. Reviewed-by: Richard Henderson r~

[PATCH v4 20/20] target/riscv: Enable uxl field write

2021-11-11 Thread LIU Zhiwei
Signed-off-by: LIU Zhiwei --- target/riscv/cpu_bits.h | 2 ++ target/riscv/csr.c | 8 +--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 9913fa9f77..5106f0e769 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv