On Fri, Nov 12, 2021 at 2:14 AM LIU Zhiwei <zhiwei_...@c-sky.com> wrote:
>
> Signed-off-by: LIU Zhiwei <zhiwei_...@c-sky.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu_bits.h | 2 ++
> target/riscv/csr.c | 8 +++++---
> 2 files changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 9913fa9f77..5106f0e769 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -413,6 +413,8 @@ typedef enum {
> #define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */
> #define SSTATUS_MXR 0x00080000
>
> +#define SSTATUS64_UXL 0x0000000300000000ULL
> +
> #define SSTATUS32_SD 0x80000000
> #define SSTATUS64_SD 0x8000000000000000ULL
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 8f8f170768..e79532053a 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -553,15 +553,14 @@ static RISCVException write_mstatus(CPURISCVState *env,
> int csrno,
> * RV32: MPV and GVA are not in mstatus. The current plan is to
> * add them to mstatush. For now, we just don't support it.
> */
> - mask |= MSTATUS_MPV | MSTATUS_GVA;
> + mask |= MSTATUS_MPV | MSTATUS_GVA | MSTATUS64_UXL;
> }
>
> mstatus = (mstatus & ~mask) | (val & mask);
>
> if (riscv_cpu_mxl(env) == MXL_RV64) {
> - /* SXL and UXL fields are for now read only */
> + /* SXL fields are for now read only */
> mstatus = set_field(mstatus, MSTATUS64_SXL, MXL_RV64);
> - mstatus = set_field(mstatus, MSTATUS64_UXL, MXL_RV64);
> }
> env->mstatus = mstatus;
>
> @@ -840,6 +839,9 @@ static RISCVException write_sstatus(CPURISCVState *env,
> int csrno,
> target_ulong val)
> {
> target_ulong mask = (sstatus_v1_10_mask);
> + if (cpu_get_xl(env) != MXL_RV32) {
> + mask |= SSTATUS64_UXL;
> + }
> target_ulong newval = (env->mstatus & ~mask) | (val & mask);
> return write_mstatus(env, CSR_MSTATUS, newval);
> }
> --
> 2.25.1
>
>
