u-...@nongnu.org; qemu-devel@nongnu.org
> Subject: Re: [PATCH v4 1/3] target-arm: Add support for Fujitsu A64FX
>
> On Wed, Aug 18, 2021 at 08:29:15AM +, ishii.shuuic...@fujitsu.com wrote:
> >
> > We appreciate everyone's comments.
> > Before making the V5 patch, p
ches and
provide the a64fx supported bitmap.
I think this will be more clear once I get the patch posted (which I
haven't started writing yet). I'll try to get it posted by tomorrow
evening though, since I have vacation on Friday.
Thanks,
drew
>
> Best regards.
>
>
_finalize function is not called.
In which function is it appropriate to execute the modulo max_vq function
(or equivalent process)?
If We are not understanding you correctly,
We would appreciate your comments.
Best regards.
> -Original Message-
> From: Andrew Jones
> Sent: We
On Tue, Aug 17, 2021 at 05:53:34AM -1000, Richard Henderson wrote:
> On 8/17/21 5:36 AM, Andrew Jones wrote:
> > On Tue, Aug 17, 2021 at 05:23:17AM -1000, Richard Henderson wrote:
> > > On 8/17/21 1:56 AM, Andrew Jones wrote:
> > > > I guess it's fine. You could easily create a new cpu_arm_set_sve_
On 8/17/21 5:36 AM, Andrew Jones wrote:
On Tue, Aug 17, 2021 at 05:23:17AM -1000, Richard Henderson wrote:
On 8/17/21 1:56 AM, Andrew Jones wrote:
I guess it's fine. You could easily create a new cpu_arm_set_sve_vq()
which would forbid changing the properties if you wanted to, but then
we need
On Tue, Aug 17, 2021 at 05:23:17AM -1000, Richard Henderson wrote:
> On 8/17/21 1:56 AM, Andrew Jones wrote:
> > I guess it's fine. You could easily create a new cpu_arm_set_sve_vq()
> > which would forbid changing the properties if you wanted to, but then
> > we need to answer Peter's question in
On 8/17/21 1:56 AM, Andrew Jones wrote:
I guess it's fine. You could easily create a new cpu_arm_set_sve_vq()
which would forbid changing the properties if you wanted to, but then
we need to answer Peter's question in order to see if there's a
precedent for that type of property.
I don't see th
> However, by allowing the sve128, sve256, and sve512 properties to be
> specified,
> the user can explicitly change the settings (ex: sve128=off),
> but the only properties that can be set is the vector length supported by
> A64FX.
> We personally think this is a no problem.
I g
ser can explicitly change the settings (ex: sve128=off),
but the only properties that can be set is the vector length supported by
A64FX.
We personally think this is a no problem.
We would appreciate your comments.
Best regards.
> -Original Message-
> From: Andrew Jones
> Sen
On Thu, 12 Aug 2021 at 10:25, Andrew Jones wrote:
> On second thought, do we want the QMP CPU model expansion query to show
> that this CPU type has sve,sve128,sve256,sve512? If so, then our SVE work
> isn't complete, because we need those properties, set true by default, but
> forbidden from chan
On Thu, Aug 12, 2021 at 11:16:50AM +0200, Andrew Jones wrote:
> On Thu, Aug 12, 2021 at 03:04:38PM +0900, Shuuichirou Ishii wrote:
> > Add a definition for the Fujitsu A64FX processor.
> >
> > The A64FX processor does not implement the AArch32 Execution state,
> > so there are no associated AArch3
On Thu, Aug 12, 2021 at 03:04:38PM +0900, Shuuichirou Ishii wrote:
> Add a definition for the Fujitsu A64FX processor.
>
> The A64FX processor does not implement the AArch32 Execution state,
> so there are no associated AArch32 Identification registers.
>
> For SVE, the A64FX processor supports o
Add a definition for the Fujitsu A64FX processor.
The A64FX processor does not implement the AArch32 Execution state,
so there are no associated AArch32 Identification registers.
For SVE, the A64FX processor supports only 128,256 and 512bit vector lengths.
Signed-off-by: Shuuichirou Ishii
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