Re: [PATCH v3 4/6] target/loongarch: Support LoongArch32 TLB entry

2023-08-07 Thread Richard Henderson
On 8/7/23 02:45, Jiajie Chen wrote: The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to zero in LoongArch32. Signed-off-by: Jiajie Chen --- target/loongarch/cpu-csr.h| 9 + target/loongarch/tlb_helper.c | 17 - 2 files changed, 17 insertions(+),

[PATCH v3 4/6] target/loongarch: Support LoongArch32 TLB entry

2023-08-07 Thread Jiajie Chen
The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to zero in LoongArch32. Signed-off-by: Jiajie Chen --- target/loongarch/cpu-csr.h| 9 + target/loongarch/tlb_helper.c | 17 - 2 files changed, 17 insertions(+), 9 deletions(-) diff --git a/target/loo