On Tue, Nov 19, 2019 at 11:39:04AM -0500, Michael S. Tsirkin wrote:
> On Tue, Nov 19, 2019 at 11:21:10AM -0500, Peter Xu wrote:
> > On Tue, Nov 19, 2019 at 06:05:11AM -0500, Michael S. Tsirkin wrote:
> > > On Tue, Nov 19, 2019 at 08:28:12PM +0800, qi1.zh...@intel.com wrote:
> > > > From: "Zhang, Qi
On Tue, Nov 19, 2019 at 11:21:10AM -0500, Peter Xu wrote:
> On Tue, Nov 19, 2019 at 06:05:11AM -0500, Michael S. Tsirkin wrote:
> > On Tue, Nov 19, 2019 at 08:28:12PM +0800, qi1.zh...@intel.com wrote:
> > > From: "Zhang, Qi"
> > >
> > > spilt the reserved fields arrays and remove TM field from re
On Tue, Nov 19, 2019 at 06:05:11AM -0500, Michael S. Tsirkin wrote:
> On Tue, Nov 19, 2019 at 08:28:12PM +0800, qi1.zh...@intel.com wrote:
> > From: "Zhang, Qi"
> >
> > spilt the reserved fields arrays and remove TM field from reserved
> > bits
>
> Looks good to me.
> Also Cc Peter Xu.
> Also
On Tue, Nov 19, 2019 at 08:28:12PM +0800, qi1.zh...@intel.com wrote:
> From: "Zhang, Qi"
>
> spilt the reserved fields arrays and remove TM field from reserved
> bits
Looks good to me.
Also Cc Peter Xu.
Also I wonder - do we need to version this change
with the machine type? Peter what's your
From: "Zhang, Qi"
spilt the reserved fields arrays and remove TM field from reserved
bits
Changelog V1:
add descriptons
Changelog V2:
refine
Zhang, Qi (2):
intel_iommu: split the resevred fields arrays into two ones
intel_iommu: TM field should not be in reserved bits
hw/i386/intel_io
