On 7/21/23 18:08, Daniel Henrique Barboza wrote:
On 7/20/23 23:38, Nicholas Piggin wrote:
On Thu Jul 13, 2023 at 3:35 AM AEST, Shawn Anastasio wrote:
On 7/12/23 11:56 AM, Cédric Le Goater wrote:
Hello Shawn,
On 7/12/23 18:13, Shawn Anastasio wrote:
Change radix model to always generate a s
On 7/20/23 23:38, Nicholas Piggin wrote:
On Thu Jul 13, 2023 at 3:35 AM AEST, Shawn Anastasio wrote:
On 7/12/23 11:56 AM, Cédric Le Goater wrote:
Hello Shawn,
On 7/12/23 18:13, Shawn Anastasio wrote:
Change radix model to always generate a storage interrupt when the R/C
bits are not set ap
On Thu Jul 13, 2023 at 3:35 AM AEST, Shawn Anastasio wrote:
> On 7/12/23 11:56 AM, Cédric Le Goater wrote:
> > Hello Shawn,
> >
> > On 7/12/23 18:13, Shawn Anastasio wrote:
> >> Change radix model to always generate a storage interrupt when the R/C
> >> bits are not set appropriately in a PTE inst
On 7/12/23 11:56 AM, Cédric Le Goater wrote:
> Hello Shawn,
>
> On 7/12/23 18:13, Shawn Anastasio wrote:
>> Change radix model to always generate a storage interrupt when the R/C
>> bits are not set appropriately in a PTE instead of setting the bits
>> itself. According to the ISA both behaviors
Hello Shawn,
On 7/12/23 18:13, Shawn Anastasio wrote:
Change radix model to always generate a storage interrupt when the R/C
bits are not set appropriately in a PTE instead of setting the bits
itself. According to the ISA both behaviors are valid, but in practice
this change more closely matche
Change radix model to always generate a storage interrupt when the R/C
bits are not set appropriately in a PTE instead of setting the bits
itself. According to the ISA both behaviors are valid, but in practice
this change more closely matches behavior observed on the POWER9 CPU.
>From the POWER9
