On 7/12/23 11:56 AM, Cédric Le Goater wrote: > Hello Shawn, > > On 7/12/23 18:13, Shawn Anastasio wrote: >> Change radix model to always generate a storage interrupt when the R/C >> bits are not set appropriately in a PTE instead of setting the bits >> itself. According to the ISA both behaviors are valid, but in practice >> this change more closely matches behavior observed on the POWER9 CPU. > > How did you spotted this dark corner case in emulation ? Do you have > MMU unit tests ?
I'm currently porting Xen to Power and have been using QEMU's powernv model extensively for early bring up. I noticed the issue when my radix implementation worked in QEMU but failed on actual hardware since I didn't have a proper storage interrupt handler implemented. >> Signed-off-by: Shawn Anastasio <sanasta...@raptorengineering.com> > Reviewed-by: Cédric Le Goater <c...@kaod.org> Much appreciated. > Thanks, > > C. Thanks, Shawn
