gt; Thanks,
> Kinsey
>
> -Original Message-
> From: Francisco Iglesias
> Sent: Monday, July 10, 2023 09:10
> To: peter.mayd...@linaro.org
> Cc: Kinsey Moore ; qemu-devel@nongnu.org;
> phi...@linaro.org
> Subject: Re: [PATCH v2] hw/arm/xlnx: Connect secondary CGEM IRQs
3 09:10
To: peter.mayd...@linaro.org
Cc: Kinsey Moore ; qemu-devel@nongnu.org;
phi...@linaro.org
Subject: Re: [PATCH v2] hw/arm/xlnx: Connect secondary CGEM IRQs
+PMM (I think this one might have fallen throught the cracks)
Best regards,
Francisco Iglesias
On [2023 Jun 18] Sun 00:50:47, Philippe Mat
+PMM (I think this one might have fallen throught the cracks)
Best regards,
Francisco Iglesias
On [2023 Jun 18] Sun 00:50:47, Philippe Mathieu-Daudé wrote:
> On 16/6/23 16:38, Kinsey Moore wrote:
> > The Cadence GEM peripherals as configured for Zynq MPSoC and Versal
> > platforms have two prio
On 16/6/23 16:38, Kinsey Moore wrote:
The Cadence GEM peripherals as configured for Zynq MPSoC and Versal
platforms have two priority queues with separate interrupt sources for
each. If the interrupt source for the second priority queue is not
connected, they work in polling mode only. This chang
On [2023 Jun 16] Fri 09:38:03, Kinsey Moore wrote:
> The Cadence GEM peripherals as configured for Zynq MPSoC and Versal
> platforms have two priority queues with separate interrupt sources for
> each. If the interrupt source for the second priority queue is not
> connected, they work in polling mo
The Cadence GEM peripherals as configured for Zynq MPSoC and Versal
platforms have two priority queues with separate interrupt sources for
each. If the interrupt source for the second priority queue is not
connected, they work in polling mode only. This change connects the
second interrupt source f
