[PATCH v1 1/1] target/riscv: add VILL field for vtype register macro definition

Signed-off-by: Chao Liu --- target/riscv/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 284b112821..fc286484b8 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -170,7 +170,8 @@ FIELD(VTYPE, VSEW, 3, 3) FIELD(VT

Re: [PATCH v1 1/1] target/riscv: add VILL field for vtype register macro definition

On 12/11/24 07:47, Chao Liu wrote: Signed-off-by: Chao Liu --- target/riscv/cpu.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 284b112821..fc286484b8 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -170,7 +170,