On 5/14/25 22:33, Daniel Henrique Barboza wrote:
Richard,
On 4/25/25 12:23 PM, Richard Henderson wrote:
Do not examine a random host return address, but
properly compute the next pc for the guest cpu.
Fixes: f18637cd611 ("RISC-V: Add misa runtime write support")
Signed-off-by: Richard Henderso
Richard,
On 4/25/25 12:23 PM, Richard Henderson wrote:
Do not examine a random host return address, but
properly compute the next pc for the guest cpu.
Fixes: f18637cd611 ("RISC-V: Add misa runtime write support")
Signed-off-by: Richard Henderson
---
target/riscv/csr.c | 22 +
On Wed, Apr 30, 2025 at 12:34 AM Richard Henderson
wrote:
>
> On 4/25/25 08:23, Richard Henderson wrote:
> > -if ((val & RVC) && (GETPC() & ~3) != 0) {
> > +/* Suppress 'C' if next instruction is not aligned. */
> > +if ((val & RVC) && (get_next_pc(env, ra) & ~3) != 0) {
>
> Bah. I pr
On 4/25/25 08:23, Richard Henderson wrote:
-if ((val & RVC) && (GETPC() & ~3) != 0) {
+/* Suppress 'C' if next instruction is not aligned. */
+if ((val & RVC) && (get_next_pc(env, ra) & ~3) != 0) {
Bah. I preserved a second bug here: not "& ~3" but "& 3".
r~
On Sat, Apr 26, 2025 at 1:26 AM Richard Henderson
wrote:
>
> Do not examine a random host return address, but
> properly compute the next pc for the guest cpu.
>
> Fixes: f18637cd611 ("RISC-V: Add misa runtime write support")
> Signed-off-by: Richard Henderson
Reviewed-by: Alistair Francis
Ali
On 25/4/25 17:23, Richard Henderson wrote:
Do not examine a random host return address, but
properly compute the next pc for the guest cpu.
Fixes: f18637cd611 ("RISC-V: Add misa runtime write support")
Signed-off-by: Richard Henderson
---
target/riscv/csr.c | 22 +-
1 fil
Do not examine a random host return address, but
properly compute the next pc for the guest cpu.
Fixes: f18637cd611 ("RISC-V: Add misa runtime write support")
Signed-off-by: Richard Henderson
---
target/riscv/csr.c | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
di
