Re: [PATCH 7/7] target/riscv: Fix write_misa vs aligned next_pc

[Richard Henderson]

On 4/25/25 08:23, Richard Henderson wrote:

-    if ((val & RVC) && (GETPC() & ~3) != 0) {
+    /* Suppress 'C' if next instruction is not aligned. */
+    if ((val & RVC) && (get_next_pc(env, ra) & ~3) != 0) {

Bah.  I preserved a second bug here: not "& ~3" but "& 3".


r~