On 7/3/24 23:19, Xiaoyao Li wrote:
On 7/4/2024 11:14 AM, Ewan Hai wrote:
On 7/3/24 10:49, Xiaoyao Li wrote:
On 6/25/2024 5:19 PM, EwanHai wrote:
Zhaoxin and VIA CPUs handle the CMPLegacy bit in the same way
as Intel CPUs. This patch simplifies the existing logic by
using the IS_XXX_CPU macr
On 7/4/2024 11:14 AM, Ewan Hai wrote:
On 7/3/24 10:49, Xiaoyao Li wrote:
On 6/25/2024 5:19 PM, EwanHai wrote:
Zhaoxin and VIA CPUs handle the CMPLegacy bit in the same way
as Intel CPUs. This patch simplifies the existing logic by
using the IS_XXX_CPU macro and includes checks for Zhaoxin
and
On 7/3/24 10:49, Xiaoyao Li wrote:
On 6/25/2024 5:19 PM, EwanHai wrote:
Zhaoxin and VIA CPUs handle the CMPLegacy bit in the same way
as Intel CPUs. This patch simplifies the existing logic by
using the IS_XXX_CPU macro and includes checks for Zhaoxin
and VIA vendors to align their behavior wit
On 6/25/2024 5:19 PM, EwanHai wrote:
Zhaoxin and VIA CPUs handle the CMPLegacy bit in the same way
as Intel CPUs. This patch simplifies the existing logic by
using the IS_XXX_CPU macro and includes checks for Zhaoxin
and VIA vendors to align their behavior with Intel.
Signed-off-by: EwanHai
---
Zhaoxin and VIA CPUs handle the CMPLegacy bit in the same way
as Intel CPUs. This patch simplifies the existing logic by
using the IS_XXX_CPU macro and includes checks for Zhaoxin
and VIA vendors to align their behavior with Intel.
Signed-off-by: EwanHai
---
target/i386/cpu.c | 6 +++---
1 file
