On 12/13/24 10:31, Konrad, Frederic wrote:
+CC maintainers
-Original Message-
From: qemu-devel-bounces+fkonrad=amd@nongnu.org
On
Behalf Of Richard Henderson
Sent: 11 December 2024 22:43
To: qemu-devel@nongnu.org
Subject: Re: [PATCH 3/3] target/riscv: fix the trap generation for
+CC maintainers
> -Original Message-
> From: qemu-devel-bounces+fkonrad=amd@nongnu.org
> On
> Behalf Of Richard Henderson
> Sent: 11 December 2024 22:43
> To: qemu-devel@nongnu.org
> Subject: Re: [PATCH 3/3] target/riscv: fix the trap generation for
> cond
On 12/11/24 15:19, Frederic Konrad wrote:
+/*
+ * A misaligned store trap should be triggered even if the store should
+ * fail due to the reservation.
+ */
+tcg_gen_andi_tl(tmp, src1, ~((uint64_t)0) << memop_alignment_bits(mop));
The constant is incorrect for testing the lo
>From Unpriviledged ISA manual:
"For LR and SC, the Zalrsc extension requires that the address held in rs1 be
naturally aligned to the size of the operand (i.e., eight-byte aligned for
doublewords and four-byte aligned for words). If the address is not naturally
aligned, an address-misaligned exce
