On Sat, May 01, 2021 at 05:24:35PM +1000, Nicholas Piggin wrote:
> POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL],
> and it removes support for the LPCR[AIL]=0b10 mode.
>
> Reviewed-by: Cédric Le Goater
> Tested-by: Cédric Le Goater
> Signed-off-by: Nicholas Piggin
Applie
POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL],
and it removes support for the LPCR[AIL]=0b10 mode.
Reviewed-by: Cédric Le Goater
Tested-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_hcall.c| 7 -
target/ppc/cpu-qom.h|
On 4/15/21 7:28 AM, Nicholas Piggin wrote:
> Excerpts from Cédric Le Goater's message of April 15, 2021 1:54 am:
>> On 4/14/21 5:23 AM, Nicholas Piggin wrote:
>>> POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL],
>>> and it removes support for the LPCR[AIL]=0b10 mode.
>>
>> This
Excerpts from Cédric Le Goater's message of April 15, 2021 1:54 am:
> On 4/14/21 5:23 AM, Nicholas Piggin wrote:
>> POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL],
>> and it removes support for the LPCR[AIL]=0b10 mode.
>
> This looks good but it's missing the MSR_LE setting.
On 4/14/21 5:23 AM, Nicholas Piggin wrote:
> POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL],
> and it removes support for the LPCR[AIL]=0b10 mode.
This looks good but it's missing the MSR_LE setting. A part from that :
Reviewed-by: Cédric Le Goater
and
Tested-by: Cédric
POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL],
and it removes support for the LPCR[AIL]=0b10 mode.
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_hcall.c| 7 +-
target/ppc/cpu-qom.h| 2 ++
target/ppc/cpu.h| 5 ++--
target/ppc
