Excerpts from Cédric Le Goater's message of April 15, 2021 1:54 am: > On 4/14/21 5:23 AM, Nicholas Piggin wrote: >> POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL], >> and it removes support for the LPCR[AIL]=0b10 mode. > > This looks good but it's missing the MSR_LE setting. A part from that :
Oh, and lpes as well. Looks like a mis-merged from my original patch. Thanks for catching it, great. > > Reviewed-by: Cédric Le Goater <c...@kaod.org> > > and > > Tested-by: Cédric Le Goater <c...@kaod.org> Thanks, this was tested after you added the MSR_LE bit? > > distros using scv on P10 now need your patch to boot : > > "powerpc/powernv: Enable HAIL (HV AIL) for ISA v3.1 processors" > > I guess it will get merged in time. Yes, unfortunately. Real hardware crashes the same way though, so nothing to be done about it. Thanks, Nick
