Re: [PATCH 1/3] target/riscv: Optional feature to provide trapped instruction in CSRs

2020-08-12 Thread Alistair Francis
On Wed, Jul 29, 2020 at 4:29 AM Anup Patel wrote: > > The RISC-V spec allows implementations to provide trapped instruction > opcode in MTVAL/STVAL CSR for illegal/virtual instruction traps. This > is totally optional and most RISC-V implementations always set zero > in the MTVAL/STVAL CSR for ill

[PATCH 1/3] target/riscv: Optional feature to provide trapped instruction in CSRs

2020-07-29 Thread Anup Patel
The RISC-V spec allows implementations to provide trapped instruction opcode in MTVAL/STVAL CSR for illegal/virtual instruction traps. This is totally optional and most RISC-V implementations always set zero in the MTVAL/STVAL CSR for illegal/virtual instruction traps. When trapped instruction opc