On Wed, Jul 29, 2020 at 4:29 AM Anup Patel <anup.pa...@wdc.com> wrote:
>
> The RISC-V spec allows implementations to provide trapped instruction
> opcode in MTVAL/STVAL CSR for illegal/virtual instruction traps. This
> is totally optional and most RISC-V implementations always set zero
> in the MTVAL/STVAL CSR for illegal/virtual instruction traps.
>
> When trapped instruction opcode is available in MTVAL/STVAL CSR, the
> M-mode runtime firmware (and Hypervisors) can skip unprivlege access
> for reading trapped instruction opcode which in-turn will speed-up
> the illegal/virtual instruction trap handling.
>
> This patch implements RISCV_FEATURE_TINST feature which when enabled
> provides original trapped instruction opcode in MTVAL/STVAL CSRs for
> illegal/virtual instruction trap.
>
> Signed-off-by: Anup Patel <anup.pa...@wdc.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 7 +++++++
> target/riscv/cpu.h | 11 ++++++++++-
> target/riscv/cpu_helper.c | 6 ++++++
> target/riscv/translate.c | 14 +++++++++++++-
> 4 files changed, 36 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index eeb91f8513..ec098e445e 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -317,6 +317,7 @@ void restore_state_to_opc(CPURISCVState *env,
> TranslationBlock *tb,
> target_ulong *data)
> {
> env->pc = data[0];
> + env->trap_insn = data[1];
> }
>
> static void riscv_cpu_reset(DeviceState *dev)
> @@ -332,6 +333,7 @@ static void riscv_cpu_reset(DeviceState *dev)
> env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
> env->mcause = 0;
> env->pc = env->resetvec;
> + env->trap_insn = 0;
> #endif
> cs->exception_index = EXCP_NONE;
> env->load_res = -1;
> @@ -387,6 +389,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> set_feature(env, RISCV_FEATURE_PMP);
> }
>
> + if (cpu->cfg.tinst) {
> + set_feature(env, RISCV_FEATURE_TINST);
> + }
> +
> /* If misa isn't set (rv32 and rv64 machines) set it here */
> if (!env->misa) {
> /* Do some ISA extension error checking */
> @@ -487,6 +493,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
> DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
> DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
> + DEFINE_PROP_BOOL("tinst", RISCVCPU, cfg.tinst, false),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 1bb5271511..33984539d7 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -26,6 +26,12 @@
>
> #define TCG_GUEST_DEFAULT_MO 0
>
> +/*
> + * RISC-V-specific extra insn start words:
> + * 1: Original instruction opcode
> + */
> +#define TARGET_INSN_START_EXTRA_WORDS 1
> +
> #define TYPE_RISCV_CPU "riscv-cpu"
>
> #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
> @@ -70,7 +76,8 @@
> enum {
> RISCV_FEATURE_MMU,
> RISCV_FEATURE_PMP,
> - RISCV_FEATURE_MISA
> + RISCV_FEATURE_MISA,
> + RISCV_FEATURE_TINST
> };
>
> #define PRIV_VERSION_1_10_0 0x00011000
> @@ -97,6 +104,7 @@ struct CPURISCVState {
> target_ulong frm;
>
> target_ulong badaddr;
> + target_ulong trap_insn;
> target_ulong guest_phys_fault_addr;
>
> target_ulong priv_ver;
> @@ -264,6 +272,7 @@ typedef struct RISCVCPU {
> char *user_spec;
> bool mmu;
> bool pmp;
> + bool tinst;
> } cfg;
> } RISCVCPU;
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index eccd80cfef..e4bd45d66a 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -864,6 +864,12 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> case RISCV_EXCP_STORE_PAGE_FAULT:
> tval = env->badaddr;
> break;
> + case RISCV_EXCP_VIRT_INSTRUCTION_FAULT:
> + case RISCV_EXCP_ILLEGAL_INST:
> + if (riscv_feature(env, RISCV_FEATURE_TINST)) {
> + tval = env->trap_insn;
> + }
> + break;
> default:
> break;
> }
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 1d973b62e9..03954bff62 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -56,6 +56,8 @@ typedef struct DisasContext {
> to reset this known value. */
> int frm;
> bool ext_ifencei;
> + /* TCG op of the current insn_start. */
> + TCGOp *insn_start;
> } DisasContext;
>
> #ifdef TARGET_RISCV64
> @@ -717,6 +719,13 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
> /* Include the auto-generated decoder for 16 bit insn */
> #include "decode_insn16.inc.c"
>
> +static inline void decode_save_opc(DisasContext *ctx, target_ulong opc)
> +{
> + assert(ctx->insn_start != NULL);
> + tcg_set_insn_start_param(ctx->insn_start, 1, opc);
> + ctx->insn_start = NULL;
> +}
> +
> static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t
> opcode)
> {
> /* check for compressed insn */
> @@ -724,6 +733,7 @@ static void decode_opc(CPURISCVState *env, DisasContext
> *ctx, uint16_t opcode)
> if (!has_ext(ctx, RVC)) {
> gen_exception_illegal(ctx);
> } else {
> + decode_save_opc(ctx, opcode);
> ctx->pc_succ_insn = ctx->base.pc_next + 2;
> if (!decode_insn16(ctx, opcode)) {
> /* fall back to old decoder */
> @@ -734,6 +744,7 @@ static void decode_opc(CPURISCVState *env, DisasContext
> *ctx, uint16_t opcode)
> uint32_t opcode32 = opcode;
> opcode32 = deposit32(opcode32, 16, 16,
> translator_lduw(env, ctx->base.pc_next + 2));
> + decode_save_opc(ctx, opcode32);
> ctx->pc_succ_insn = ctx->base.pc_next + 4;
> if (!decode_insn32(ctx, opcode32)) {
> gen_exception_illegal(ctx);
> @@ -773,7 +784,8 @@ static void riscv_tr_insn_start(DisasContextBase *dcbase,
> CPUState *cpu)
> {
> DisasContext *ctx = container_of(dcbase, DisasContext, base);
>
> - tcg_gen_insn_start(ctx->base.pc_next);
> + tcg_gen_insn_start(ctx->base.pc_next, 0);
> + ctx->insn_start = tcg_last_op();
> }
>
> static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState
> *cpu,
> --
> 2.25.1
>
>
