On Thu, Aug 8, 2024 at 1:51 PM Yong-Xuan Wang wrote:
>
> In the section "4.7 Precise effects on interrupt-pending bits"
> of the RISC-V AIA specification defines that:
>
> If the source mode is Level1 or Level0 and the interrupt domain
> is configured in MSI delivery mode (domaincfg.DM = 1):
> The
ping
On Fri, Aug 9, 2024 at 11:28 AM Yong-Xuan Wang wrote:
>
> Hi Daniel,
>
> On Fri, Aug 9, 2024 at 5:40 AM Daniel Henrique Barboza
> wrote:
> >
> > Ccing Anup
> >
> > On 8/8/24 5:20 AM, Yong-Xuan Wang wrote:
> > > In the section "4.7 Precise effects on interrupt-pending bits"
> > > of the RISC
Hi Daniel,
On Fri, Aug 9, 2024 at 5:40 AM Daniel Henrique Barboza
wrote:
>
> Ccing Anup
>
> On 8/8/24 5:20 AM, Yong-Xuan Wang wrote:
> > In the section "4.7 Precise effects on interrupt-pending bits"
> > of the RISC-V AIA specification defines that:
> >
> > If the source mode is Level1 or Level0
Ccing Anup
On 8/8/24 5:20 AM, Yong-Xuan Wang wrote:
In the section "4.7 Precise effects on interrupt-pending bits"
of the RISC-V AIA specification defines that:
If the source mode is Level1 or Level0 and the interrupt domain
is configured in MSI delivery mode (domaincfg.DM = 1):
The pending bit
In the section "4.7 Precise effects on interrupt-pending bits"
of the RISC-V AIA specification defines that:
If the source mode is Level1 or Level0 and the interrupt domain
is configured in MSI delivery mode (domaincfg.DM = 1):
The pending bit is cleared whenever the rectified input value is
low,
